Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice

A method for making a semiconductor device comprising:

• forming a hyper-abrupt junction region on a substrate and comprising
• a first semiconductor layer having a first conductivity type,
• an intrinsic semiconductor layer on the first semiconductor layer,
• a superlattice layer on the intrinsic semiconductor layer, the superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and
• a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type,
• the first, second, and intrinsic semiconductor layers and the superlattice layer being U-shaped;
• forming a gate dielectric layer on the second semiconductor layer of the hyper-abrupt junction region;
• forming a gate electrode on the gate dielectric layer;
• and
• forming spaced apart source and drain regions coupled to the hyper-abrupt junction region;
• the spaced apart source and drain regions having the second conductivity type, and the first, second, and intrinsic semiconductor layers having a thickness in a range of 50 nm to 300 nm.

A method for making a

• semiconductor device comprising:
• forming a hyper-abrupt junction region on a substrate and comprising
• a first semiconductor layer having a first conductivity type,
• a superlattice layer on the first semiconductor layer, the superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions,
• an intrinsic semiconductor layer on the superlattice layer, and
• a second semiconductor layer on the intrinsic semiconductor layer and having a second conductivity type different than the first conductivity type,
• the first, second, and intrinsic semiconductor layers and the superlattice layer being U-shaped;
• forming a gate dielectric layer on the second semiconductor layer of the hyper-abrupt junction region;
• forming a gate electrode on the gate dielectric layer;
• and
• forming spaced apart source and drain regions coupled to the hyper-abrupt junction region.