# US 10,873,483 B2 · Semiconductor device and memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,873,483 B2 - Document ID: US10873483B2 - Status: Granted - Kind: B2 - Application number: 16/590,191 - Filed: 2019-10-01 - Published: 2020-01-30 - Granted: 2020-12-22 - Earliest claimed: 2016-09-13 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Kensuke Yamamoto; Kosuke Yanagidaira - Web page: https://patentgrep.com/patent/US10873483B2 ## CPC - H04L 25/0278: {Arrangements for impedance matching} - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/409: Read-write [R-W] circuits - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C 29/022: {in I/O circuitry} - G11C 29/028: {with adaption or trimming of parameters} - H03K 19/0005: {Modifications of input or output impedance} - H03K 19/17764: for reliability - G11C 2207/105: Aspects related to pads, pins or terminals - G11C 2207/2254: Calibration - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal. ## Claims ### Claim 1 A semiconductor device configured to communicate with a controller, the semiconductor device comprising: a first chip that includes a first circuit having a first output terminal; and a second chip that includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line, wherein upon receipt of a first command, the first circuit calibrates an output impedance at the first output terminal through a first calibration operation, and the first circuit issues a signal indicating that the first chip is in a ready state during the first calibration operation, upon receipt of a second command after the first calibration operation is performed, the second circuit calibrates an output impedance at the second output terminal through a second calibration operation based on the output impedance at the first output terminal, and a duration of the second calibration operation is shorter than a duration of the first calibration operation. ### Claim 2 A semiconductor device configured to communicate with a controller, the semiconductor device comprising: a first chip that includes a first circuit having a first output terminal; and a second chip that includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line, wherein the first chip: upon receipt of a first command, calibrates an output impedance at the first output terminal through a first calibration operation, transmits to the controller a signal indicating that the first chip is in a busy state upon starting the first calibration operation, and transmits to the controller a signal indicating that the first chip is in a ready state upon completion of the first calibration operation, the second chip: upon receipt of a second command after the first calibration operation is performed, calibrates an output impedance at the second output terminal through a second calibration operation based on the output impedance at the first output terminal, transmits to the controller a signal indicating that the second chip is in the busy state upon starting the second calibration operation, and transmits to the controller a signal indicating that the second chip is in the ready state upon completion of the second calibration operation, and a duration of the second calibration operation is shorter than a duration of the first calibration operation. ### Claim 3 A semiconductor device configured to communicate with a controller, the semiconductor device comprising: a first chip that includes a first circuit including a first output terminal; and a second chip that includes a second circuit including a second output terminal, which is electrically connected to the first output terminal via a first signal line, wherein upon receipt of a first command, the first circuit calibrates an output impedance at the first output terminal through a first calibration operation, upon receipt of a second command after the first calibration operation is performed, the second circuit calibrates an output impedance at the second output terminal through a second calibration operation based on the output impedance at the first output terminal, a duration of the second calibration operation is shorter than a duration of the first calibration operation, the first circuit further includes: a first pull-up circuit having a first terminal to which a first voltage is supplied, and a second terminal electrically connected to the first output terminal, and a first pull-down circuit having a first terminal to which a second voltage smaller than the first voltage is supplied and a second terminal electrically connected to the first output terminal, the second circuit further includes: a second pull-up circuit having a first terminal to which the first voltage is supplied, and a second terminal electrically connected to the second output terminal, a second pull-down circuit having a first terminal to which the second voltage is supplied, and a second terminal electrically connected to the second output terminal, and a comparator having a first terminal to which a voltage of the second output terminal is supplied and a second terminal to which a third voltage between the first voltage and the second voltage is supplied, and the second calibration operation includes: a first operation during which the first pull-up circuit and the second pull-down circuit enter an ON state while the first pull-down circuit and the second pull-up circuit enter an OFF state, and a second operation during which the second pull-up circuit and the first pull-down circuit enter an ON state while the second pull-down circuit and the first pull-up circuit enter an OFF state. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein during the first operation, the second circuit calibrates a resistance value of the second pull-down circuit based on a comparison result of the comparator that compares the voltage of the second output terminal with the third voltage. ### Claim 5 (depends on 3) The semiconductor device according to claim 3, wherein during the second operation, the second circuit calibrates a resistance value of the second pull-up circuit based on a comparison result of the comparator that compares the voltage of the second output terminal with the third voltage. ### Claim 6 (depends on 3) The semiconductor device according to claim 3, wherein the second pull-up circuit includes first and second transistors which are connected in parallel between a voltage supply supplying the first voltage and the second output terminal, and the first and second transistors have different resistance values in an ON state. ### Claim 7 (depends on 3) The semiconductor device according to claim 3, wherein the second pull-down circuit includes third and fourth transistors which are connected in parallel between a voltage supply supplying the second voltage and the second output terminal, and the third and fourth transistors have different resistance values in an ON state. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, further comprising: a third chip that includes a third circuit having a third output terminal, which is electrically connected to a fourth output terminal of the first chip via a second signal line, wherein upon receipt of a third command after the first calibration operation is performed, the third circuit calibrates an output impedance at the third output terminal through a third calibration operation based on an output impedance at the fourth output terminal. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the second and third calibration operations are performed in parallel. ### Claim 10 (depends on 8) The semiconductor device according to claim 8, wherein the second and third calibration operations are performed in series. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the second command includes address information that identifies the first chip. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the first chip generates calibration result information based on a calibration result of the first calibration operation, and the second calibration operation includes adjusting the output impedance of the second output terminal based on the calibration result information. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the first circuit includes: a first pull-up circuit having a first terminal to which a first voltage is supplied, and a second terminal electrically connected to the first output terminal, and a first pull-down circuit having a first terminal to which a second voltage smaller than the first voltage is supplied and a second terminal electrically connected to the first output terminal, and the calibration result information includes: a first information corresponding to a resistance value of the first pull-up circuit, and a second information corresponding to a resistance value of the first pull-down circuit. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the second circuit includes: a second pull-up circuit having a first terminal to which the first voltage is supplied, and a second terminal electrically connected to the second output terminal, and a second pull-down circuit having a first terminal to which the second voltage is supplied, and a second terminal electrically connected to the second output terminal, and a resistance value of the second pull-up circuit is set based on the first information, and a resistance value of the second pull-down circuit is set based on the second information. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the first and second information each include a digital-to-analog converter (DAC) value. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein after the first command is received, the first calibration operation is carried out without any control from the controller. ### Claim 17 A memory system comprising: a semiconductor device including: a first chip that includes a first circuit having a first output terminal, and a second chip that includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line; and a controller electrically connected to the first and second chips via the first signal line and configured to issue a first command and a second command after the first command, wherein upon receipt of the first command, the first circuit calibrates an output impedance at the first output terminal through a first calibration operation, and the first chip generates calibration result information based on a calibration result of the first calibration operation and transmits the generated calibration result information to the controller, upon receipt of the second command, the second circuit calibrates an output impedance at the second output terminal through a second calibration operation based on the output impedance at the first output terminal, the second calibration operation including adjusting the output impedance of the second output terminal based on the calibration result information received from the controller, and a duration of the second calibration operation is shorter than a duration of the first calibration operation. ### Claim 18 (depends on 17) The memory system according to claim 17, wherein the semiconductor device further includes a third chip having a third circuit having a third output terminal, which is electrically connected to a fourth output terminal of the first chip via a second signal line, the controller is further configured to issue a third command after the first command, and upon receipt of the third command, the third circuit calibrates an output impedance at the third output terminal through a third calibration operation based on an output impedance at the fourth output terminal.