# US 10,873,444 B2 · Frequency/phase lock detector for clock and data recovery circuits

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- Number: US 10,873,444 B2
- Document ID: US10873444B2
- Status: Granted
- Kind: B2
- Application number: 16/831,867
- Filed: 2020-03-27
- Published: 2020-07-16
- Granted: 2020-12-22
- Earliest claimed: 2018-09-12
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Abishek Manian; Michael Gerald Vrazel
- Web page: https://patentgrep.com/patent/US10873444B2

## CPC

- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L 7/095: using a lock detector (H03L7/087 takes precedence)
- H04L 7/0004: {Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A circuit includes a phase and frequency detector circuit to generate a first phase detect signal indicative of whether a polarity of a first clock is the same as a polarity of a second clock upon occurrence of an edge of a data signal. The second clock being 90 degrees out of phase with respect to the first clock. A lock detect circuit determines, based on the first phase detect signal, that a third clock is one of frequency and phase locked to the data signal, frequency and quadrature locked to the data signal, and not frequency locked to the data signal.

## Claims

### Claim 1

A circuit, comprising:
a first phase detector circuit to generate a first phase detect signal indicative of whether a first clock is early or late with respect to a data signal;
a second phase detector circuit to generate a second phase detect signal indicative of whether a second clock is early or late with respect to the data signal, the second clock being 90 degrees out of phase with respect to the first clock; and
a counter to count the second phase detect signal to generate a count value.

### Claim 2 (depends on 1)

The circuit of claim 1, further comprising a power gate circuit to disable power to the second phase detector circuit.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein the counter comprises a toggle counter coupled to a ripple counter.

### Claim 4 (depends on 2)

The circuit of claim 2, further comprising a frequency detector and the power gate circuit is to disable power to the frequency detector based upon on the second phase detect signal.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein the power gate circuit is to disable power to the frequency detector and to the second phase detector circuit based on the second phase detect signal.