# US 10,873,443 B1 · Generating lower frequency multi-phase clocks using single high-frequency multi-phase divider

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- Number: US 10,873,443 B1
- Document ID: US10873443B1
- Status: Granted
- Kind: B1
- Application number: 16/457,559
- Filed: 2019-06-28
- Granted: 2020-12-22
- Earliest claimed: 2019-06-28
- Assignees: Cadence Design Systems, Inc.
- Applicants: Cadence Design Systems, Inc.
- Inventors: Jeremy Walker; Hiu Ming Lam; Mohammad Ranjbar
- Web page: https://patentgrep.com/patent/US10873443B1

## CPC

- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C 27/02: Sample-and-hold arrangements (G11C27/04 takes precedence)
- H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00)
- H04J 3/0685: {Clock or time synchronisation in a node; Intranode synchronisation}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)

## Abstract

According to certain aspects, the present embodiments are directed generally to data communication systems, and more particularly to generating multi-phase clocks in a SerDes system. Embodiments provide SerDes components and methods that are capable of generating multiple different sampling frequencies for parallelizing serial data from a single high speed clock. These and other embodiments can be implemented with circuits that are relatively small and low-power as compared to conventional approaches.

## Claims

### Claim 1

A serializer-deserializer transceiver, comprising:
an initial divider that receives an input clock having a first frequency, wherein the initial divider comprises a plurality of series-interconnected latches all clocked by the input clock, and wherein each of the latches produces a respective one of a plurality of first clocks, each of the first clocks having a second frequency that is a first integer fraction of the first frequency and being spaced apart in time from each other by a first phase spacing that less than one period of the first frequency by operation of the series-interconnected latches all being clocked by the input clock; and
a subsequent divider that is coupled to receive and combine the plurality of first clocks from the plurality of series-interconnected latches of the initial divider to thereby produce a plurality of second clocks, each of the second clocks having a third frequency that is a second integer fraction of the second frequency.

### Claim 2 (depends on 1)

The device of claim 1, wherein the plurality of first clocks are generated based on rising and falling edges of the input clock, and wherein the first phase spacing is one-half of a period of the input clock.

### Claim 3 (depends on 1)

The device of claim 1, wherein a number of the latches is the same as a number of the plurality of first clocks.

### Claim 4 (depends on 1)

The device of claim 1, wherein the subsequent divider comprises a chain of flip-flops, each of the flip-flops being clocked by a separate one of the plurality of first clocks.

### Claim 5 (depends on 4)

The device of claim 4, wherein a number of the flip-flops is the same as a number of the plurality of second clocks.

### Claim 6 (depends on 4)

The device of claim 4, wherein the subsequent divider further includes a divider that divides one of the first plurality of clocks to produce an output signal that is provided to a D-input of the chain of flip-flops.

### Claim 7 (depends on 1)

The device of claim 1, further comprising circuitry to cause the plurality of second clocks to have a predetermined duty cycle.

### Claim 8 (depends on 7)

The device of claim 7, wherein the circuitry includes another flip-flop that receives an output of one of the chain of flip-flops and generates one of the plurality of second clocks, the another flip-flop being clocked by a selected one of the plurality of first clocks.

### Claim 9

A method for generating sampling clocks in a serializer-deserializer transceiver, comprising:
receiving an input clock having a first frequency;
initially dividing the input clock to simultaneously produce a plurality of first clocks, each of the first clocks having a second frequency that is a first integer fraction of the first frequency and being spaced apart in time from each other by a first phase spacing that less than one period of the first frequency, wherein initially dividing comprises obtaining each of the plurality of first clocks from a respective one of a series of interconnected latches, wherein all of the latches are clocked by the input clock; and
subsequently producing, by receiving and combining the plurality of first clocks from the series of interconnected latches of the initial divider, a plurality of second clocks, each of the second clocks having a third frequency that is a second integer fraction of the second frequency.

### Claim 10 (depends on 9)

The method of claim 9, wherein the plurality of first clocks are generated based on rising and falling edges of the input clock, and wherein the first phase spacing is one-half of a period of the input clock.

### Claim 11 (depends on 9)

The method of claim 9, wherein a number of the latches is the same as a number of the plurality of first clocks.

### Claim 12 (depends on 9)

The method of claim 9, wherein subsequently producing comprises obtaining the second plurality of clocks from a chain of flip-flops, each of the flip-flops being clocked by a separate one of the plurality of first clocks.

### Claim 13 (depends on 12)

The method of claim 12, wherein a number of the flip-flops is the same as a number of the plurality of second clocks.

### Claim 14 (depends on 12)

The method of claim 12, wherein subsequently producing further includes dividing one of the plurality of clocks to produce an output signal that is provided to a D-input of the chain of flip-flops.

### Claim 15 (depends on 9)

The method of claim 9, further comprising causing the plurality of second clocks to have a predetermined duty cycle.

### Claim 16 (depends on 1)

The device of claim 1, further comprising samplers that receive the plurality of second clocks and input data and that sample the input data at times defined by the plurality of second clocks.

### Claim 17 (depends on 9)

The method of claim 9, further comprising:
receiving, by a sampler, the plurality of second clocks and input data; and
sampling, by the sampler, the input data at times defined by the plurality of second clocks.