# US 10,873,341 B2 · Capacitor array, successive approximation register analog-to-digital converter and capacitor array board

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- Number: US 10,873,341 B2
- Document ID: US10873341B2
- Status: Granted
- Kind: B2
- Application number: 16/628,977
- Filed: 2018-09-19
- Published: 2020-05-21
- Granted: 2020-12-22
- Earliest claimed: 2017-09-20
- Assignees: Radiawave Technologies Co., Ltd.
- Applicants: Radiawave Technologies Co., Ltd.
- Inventors: Xiaofeng Guo; Haigang Feng; Jon Sweat Duster; Yulin Tan; Ning Zhang
- Web page: https://patentgrep.com/patent/US10873341B2

## CPC

- H03M 1/466: {using switched capacitors}
- H03M 1/687: {Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type}
- H03M 1/46: with digital/analogue converter for supplying reference values to converter
- H03M 1/804: {with charge redistribution}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

The present disclosure relates to a capacitor array for an analog-to-digital converter, a successive approximation register analog-to-digital converter and a capacitor array board. The capacitor array includes a control logic generation circuit, a control code logic conversion circuit, a first sub-capacitor array and a second sub-capacitor array configured to form different regions of a high-order bit region and a low-order bit region. In the present disclosure, the capacitances of the second capacitor units are equal, so that the second capacitor units can be sequentially switched. Thus, no matter which bit in the second binary code changes, it will not cause a large number of the second capacitor units to switch together, thereby reducing conversion error. In addition, the capacitor array is divided in regions, which avoids the problem of a large number of parallel branches in case where only the second sub-capacitor array is arranged.

## Claims

### Claim 1

A capacitor array for an analog-to-digital converter, comprising a control logic generation circuit, a control code logic conversion circuit, a first sub-capacitor array and a second sub-capacitor array that are configured to form different regions of a high-order bit region and a low-order bit region; wherein:
the first sub-capacitor array comprises a plurality of first capacitor units and a plurality of first switches, the plurality of first capacitor units are sequentially arranged according to binary weighted capacitances from a least significant bit to a most significant bit, the plurality of first capacitor units are connected in parallel; each of the plurality of first capacitor units is connected to the control logic generation circuit via one of the plurality of first switches; the control logic generation circuit is configured to output a first binary code corresponding to the first sub-capacitor array to the plurality of first switches, to control switching states of the plurality of first switches;
the second sub-capacitor array comprises a plurality of second capacitor units arranged in parallel and a plurality of second switches, each of the plurality of second capacitor units is connected to the control code logic conversion circuit via one of the plurality of second switches; the control code logic conversion circuit is connected to the control logic generation circuit; capacitances of the plurality of second capacitor units are equal;
the control logic generation circuit is configured to output a second binary code corresponding to the second sub-capacitor array; the control code logic conversion circuit is configured to convert the second binary code to a thermometer code, and output the thermometer code to the plurality of second switches, to control switching states of the plurality of second switches.

### Claim 2 (depends on 1)

The capacitor array according to claim 1, wherein:
the first sub-capacitor array is configured as a capacitor array for the low-order bit region;
the second sub-capacitor array is configured as a capacitor array for the high-order bit region; and
a capacitance of the second capacitor unit at a least significant bit in the high-order bit region is twice as a maximum value of capacitances of the first capacitor units.

### Claim 3 (depends on 2)

The capacitor array according to claim 2, wherein:
the first sub-capacitor array and the second sub-capacitor array are connected in parallel;
a binary code corresponding to the plurality of first capacitor units and the plurality of second capacitor units comprises M bits, and a sum of capacitances of the plurality of first capacitor units and the plurality of second capacitor units is 2M−1 times the unit capacitance;
the number of the plurality of first capacitor units is N, and a sum of capacitances of the plurality of first capacitor units is 2N−1 times the unit capacitance; and
the number of the plurality of second capacitor units is 2M-N−1, and a sum of capacitances of the second capacitor units is 2M−2N times the unit capacitance.

### Claim 4 (depends on 1)

The capacitor array according to claim 1, wherein the number of the plurality of second capacitor units is 15, 31, or 63.

### Claim 5 (depends on 3)

The capacitor array according to claim 3, wherein the first sub-capacitor array comprises two of the plurality of first capacitor units, and the second sub-capacitor array comprises thirty-one of the plurality of second capacitor units.

### Claim 6 (depends on 1)

A successive approximation register analog-to-digital converter, comprising a comparator, a register connected to an output end of the comparator, and a capacitor array for an analog-to-digital converter according to claim 1; wherein,
the capacitor array for the analog-to-digital converter is connected to an input end of the comparator.

### Claim 7 (depends on 2)

A successive approximation register analog-to-digital converter, comprising a comparator, a register connected to an output end of the comparator, and a capacitor array for an analog-to-digital converter according to claim 2; wherein,
the capacitor array for the analog-to-digital converter is connected to an input end of the comparator.

### Claim 8 (depends on 3)

A successive approximation register analog-to-digital converter, comprising a comparator, a register connected to an output end of the comparator, and a capacitor array for an analog-to-digital converter according to claim 3; wherein,
the capacitor array for the analog-to-digital converter is connected to an input end of the comparator.

### Claim 9 (depends on 4)

A successive approximation register analog-to-digital converter, comprising a comparator, a register connected to an output end of the comparator, and a capacitor array for an analog-to-digital converter according to claim 4; wherein,
the capacitor array for the analog-to-digital converter is connected to an input end of the comparator.

### Claim 10 (depends on 5)

A successive approximation register analog-to-digital converter, comprising a comparator, a register connected to an output end of the comparator, and a capacitor array for an analog-to-digital converter according to claim 5; wherein,
the capacitor array for the analog-to-digital converter is connected to an input end of the comparator.

### Claim 11 (depends on 6)

The successive approximation register analog-to-digital converter according to claim 6, wherein a digital signal output by the successive approximation register analog-to-digital converter comprises twelve bits; wherein:
the twelve bits comprises seven high-order bits and five low-order bits; and
a capacitor array corresponding to the seven high-order bits is the capacitor array for the analog-to-digital converter.

### Claim 12 (depends on 7)

The successive approximation register analog-to-digital converter according to claim 7, wherein a digital signal output by the successive approximation register analog-to-digital converter comprises twelve bits; wherein:
the twelve bits comprises seven high-order bits and five low-order bits; and
a capacitor array corresponding to the seven high-order bits is the capacitor array for the analog-to-digital converter.

### Claim 13 (depends on 8)

The successive approximation register analog-to-digital converter according to claim 8, wherein a digital signal output by the successive approximation register analog-to-digital converter comprises twelve bits; wherein:
the twelve bits comprises seven high-order bits and five low-order bits; and
a capacitor array corresponding to the seven high-order bits is the capacitor array for the analog-to-digital converter.

### Claim 14 (depends on 9)

The successive approximation register analog-to-digital converter according to claim 9, wherein a digital signal output by the successive approximation register analog-to-digital converter comprises twelve bits; wherein:
the twelve bits comprises seven high-order bits and five low-order bits; and
a capacitor array corresponding to the seven high-order bits is the capacitor array for the analog-to-digital converter.

### Claim 15 (depends on 10)

The successive approximation register analog-to-digital converter according to claim 10, wherein a digital signal output by the successive approximation register analog-to-digital converter comprises twelve bits; wherein:
the twelve bits comprises seven high-order bits and five low-order bits; and
a capacitor array corresponding to the seven high-order bits is the capacitor array for the analog-to-digital converter.

### Claim 16 (depends on 1)

A capacitor array board, wherein:
a second sub-capacitor array in a capacitor array for an analog-to-digital converter according to claim 1 is arranged on the capacitor array board;
the capacitor array board comprises a substrate, a plurality of second capacitor units of the second sub-capacitor array are arranged on the substrate along a horizontal direction;
each of the plurality of second capacitor units comprises a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor, wherein the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are connected in parallel and each has a unit capacitance;
upper plates of the first capacitors in the plurality of second capacitor units are connected in series, a plurality of second switches in the second sub-capacitor array are in a one-to-one correspondence with the plurality of second capacitor units, and lower plates of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor in each of the plurality of second capacitor units are connected to the corresponding second switch.

### Claim 17 (depends on 16)

The capacitor array board according to claim 16, wherein:
the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor in each of the second capacitor units are arranged with the corresponding second switch along a straight line; and
the plurality of second capacitor units are arranged on the substrate in parallel.

### Claim 18 (depends on 16)

The capacitor array board according to claim 16, wherein:
the first sub-capacitor array is configured as a capacitor array for the low-order bit region;
the second sub-capacitor array is configured as a capacitor array for the high-order bit region; and
a capacitance of the second capacitor unit at a least significant bit in the high-order bit region is twice as a maximum value of capacitances of the first capacitor units.

### Claim 19 (depends on 18)

The capacitor array board according to claim 18, wherein:
the first sub-capacitor array and the second sub-capacitor array are connected in parallel;
a binary code corresponding to the plurality of first capacitor units and the plurality of second capacitor units comprises M bits, and a sum of capacitances of the plurality of first capacitor units and the plurality of second capacitor units is 2M−1 times the unit capacitance;
the number of the plurality of first capacitor units is N, and a sum of capacitances of the plurality of first capacitor units is 2N−1 times the unit capacitance; and
the number of the plurality of second capacitor units is 2M-N−1, and a sum of capacitances of the second capacitor units is 2M−2N times the unit capacitance.

### Claim 20 (depends on 16)

The capacitor array board according to claim 16, wherein the number of the second capacitor units is 15, 31, or 63.