# US 10,873,337 B2 · Electronic circuit including pipeline converting circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,873,337 B2 - Document ID: US10873337B2 - Status: Granted - Kind: B2 - Application number: 16/798,716 - Filed: 2020-02-24 - Published: 2020-08-27 - Granted: 2020-12-22 - Earliest claimed: 2019-02-25 - Assignees: Korea Advanced Institute of Science and Technology - Applicants: Korea Advanced Institute of Science and Technology - Inventors: Seung-Tak Ryu; Minjae Seo - Web page: https://patentgrep.com/patent/US10873337B2 ## CPC - H03M 1/002: {Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed} - H03M 1/164: {the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence)} - H03M 1/0695: {using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type} - H03M 1/1295: {Clamping, i.e. adjusting the DC level of the input signal to a predetermined value} - H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An electronic circuit includes a first converting circuit, an amplifying circuit, and a second converting circuit. The first converting circuit outputs a first residual voltage associated with converting an analog signal into a first digital signal and a second residual voltage generated based on the first residual voltage. The amplifying circuit generates a third residual voltage by amplifying the first residual voltage through an amplifying path during a first time duration and generates a fourth residual voltage by amplifying the second residual voltage through the amplifying path during a second time duration after the first time duration. The second converting circuit generates a second digital signal associated with the analog signal by performing an interpolation operation based on the third residual voltage and the fourth residual voltage. ## Claims ### Claim 1 An electronic circuit comprising: a first converting circuit configured to output a first residual voltage associated with converting an analog signal into a first digital signal and to output a second residual voltage generated based on the first residual voltage; an amplifying circuit configured to generate a third residual voltage by amplifying the first residual voltage through an amplifying path during a first time duration and to generate a fourth residual voltage by amplifying the second residual voltage through the amplifying path during a second time duration after the first time duration; and a second converting circuit configured to generate a second digital signal associated with the analog signal by performing an interpolation operation based on the third residual voltage and the fourth residual voltage. ### Claim 2 (depends on 1) The electronic circuit of claim 1, wherein the second residual voltage is generated as energy stored in a first capacitive element varies based on the first residual voltage. ### Claim 3 (depends on 1) The electronic circuit of claim 1, wherein the first residual voltage is generated as energy stored in a second capacitive element varies based on the analog signal. ### Claim 4 (depends on 1) The electronic circuit of claim 1, wherein the second converting circuit is further configured to: store energy in second capacitive elements based on the third residual voltage and store energy in third capacitive elements based on the fourth residual voltage. ### Claim 5 (depends on 1) The electronic circuit of claim 1, wherein the second converting circuit is further configured to: compare target levels of a voltage generated based on the third residual voltage and the fourth residual voltage with a reference level. ### Claim 6 (depends on 5) The electronic circuit of claim 5, wherein the second digital signal indicates data obtained by collecting comparison results of comparing the target levels and the reference level. ### Claim 7 (depends on 1) The electronic circuit of claim 1, further comprising: an error correction circuit configured to generate a third digital signal corresponding to the analog signal, based on the first digital signal and the second digital signal. ### Claim 8 (depends on 7) The electronic circuit of claim 7, wherein the error correction circuit is further configured to: correct the second digital signal based on the first digital signal. ### Claim 9 An electronic circuit comprising: a first converting circuit configured to output a first residual voltage associated with converting an analog signal into a first digital signal and to output a second residual voltage generated as energy stored in a first capacitive element varies based on the first residual voltage; and a second converting circuit configured to perform an interpolation operation based on a third residual voltage and a fourth residual voltage and to output a second digital signal associated with the analog signal, wherein the third residual voltage and the fourth residual voltage are obtained by respectively amplifying the first residual voltage and the second residual voltage through one amplifying path. ### Claim 10 (depends on 9) The electronic circuit of claim 9, wherein a magnitude of the first residual voltage is associated with a data value of the second digital signal, and a sum of the magnitude of the first residual voltage and a magnitude of the second residual voltage is associated with a least significant bit of the first digital signal. ### Claim 11 (depends on 9) The electronic circuit of claim 9, wherein the first residual voltage is generated as energy stored in a second capacitive element varies based on the analog signal. ### Claim 12 (depends on 11) The electronic circuit of claim 11, wherein a magnitude of the energy stored in the first capacitive element is determined based on comparison between a level of a voltage generated based on the energy stored in the second capacitive element and a reference level. ### Claim 13 (depends on 9) The electronic circuit of claim 9, wherein the first converting circuit is further configured to: output the first residual voltage during a first time duration and output the second residual voltage during a second time duration after the first time duration. ### Claim 14 (depends on 9) The electronic circuit of claim 9, wherein the interpolation operation includes an operation associated with binary search logic. ### Claim 15 An electronic circuit comprising: a first converting circuit configured to output a first residual voltage generated as an analog signal is converted into first bits of a first digital signal and a second residual voltage generated based on the first residual voltage; an amplifying circuit configured to generate a third residual voltage by amplifying the first residual voltage through an amplifying path and to generate a fourth residual voltage by amplifying the second residual voltage through the amplifying path; and a second converting circuit configured to generate second bits of the first digital signal, based on energy stored in first capacitive elements based on the third residual voltage and energy stored in second capacitive elements based on the fourth residual voltage. ### Claim 16 (depends on 15) The electronic circuit of claim 15, wherein the second converting circuit is further configured to: generate a second digital signal based on comparison between a first target level of a target voltage generated based on the energy stored in the first capacitive element and the energy stored in the second capacitive element and a reference level. ### Claim 17 (depends on 16) The electronic circuit of claim 16, wherein the second converting circuit is further configured to: generate the second digital signal further based on comparison between a second target level of the target voltage and the reference level, when the first target level is smaller than the reference level, and wherein the second target level is smaller than the first target level. ### Claim 18 (depends on 17) The electronic circuit of claim 17, wherein the second converting circuit is further configured to: generate the second digital signal further based on comparison between a third target level of the target voltage and the reference level, when the first target level is greater than the reference level, and wherein the third target level is greater than the first target level. ### Claim 19 (depends on 18) The electronic circuit of claim 18, wherein the first target level, the second target level, and the third target level are determined based on binary search logic. ### Claim 20 (depends on 15) The electronic circuit of claim 15, wherein a ratio between element values of the first capacitive elements and element values of the second capacitive elements are determined based on binary search logic.