# US 10,873,336 B2 · Track and hold circuits for high speed and interleaved ADCs

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- Number: US 10,873,336 B2
- Document ID: US10873336B2
- Status: Granted
- Kind: B2
- Application number: 16/795,503
- Filed: 2020-02-19
- Published: 2020-06-18
- Granted: 2020-12-22
- Earliest claimed: 2017-10-27
- Assignees: Analog Devices, Inc.
- Applicants: Analog Devices, Inc.
- Inventors: Ahmed Mohamed Abdelatty Ali; Frank Murden; Peter Delos; Ralph D. Moore
- Web page: https://patentgrep.com/patent/US10873336B2

## CPC

- H03M 1/002: {Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed}
- H03M 1/1033: {over the full range of the converter, e.g. for correcting differential non-linearity}
- H03H 7/42: Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
- H03M 1/0639: {using dither, e.g. using triangular or sawtooth waveforms (for increasing resolution H03M1/201)}
- H03M 1/1009: {Calibration}
- H03M 1/1215: {using time-division multiplexing}
- H03H 7/38: Impedance-matching networks
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.

## Claims

### Claim 1

A track-and-hold circuit comprising:
a balun to convert a single-ended signal to a differential signal and to output the differential signal on a first signal path and a second signal path;
a first buffer in the first signal path;
a second buffer in the second signal path;
a first sampling network coupled with an output of the first buffer, wherein the first sampling network includes dither injection;
a second sampling network coupled with an output of the second buffer, wherein the second sampling network includes dither injection; and
a discrete-time amplifier coupled with an output of the first and second sampling networks.

### Claim 2 (depends on 1)

The track-and-hold circuit of claim 1, wherein the balun is to convert the single-ended signal to the differential signal if the single-ended signal has a frequency above a threshold.

### Claim 3 (depends on 1)

The track-and-hold circuit of claim 1, wherein the first sampling network, the second sampling network, and the discrete-time amplifier are operable to provide conversion from a single-ended signal to a differential signal.

### Claim 4 (depends on 1)

The track-and-hold circuit of claim 1, wherein the discrete-time amplifier is an open-loop amplifier.

### Claim 5 (depends on 1)

The track-and-hold circuit of claim 1, further comprising a first matching network that is to match an impedance of the balun to an impedance of the first buffer.

### Claim 6 (depends on 1)

The track-and-hold circuit of claim 1, further comprising a chopper, wherein the chopper is to inject a multiplicative dither.

### Claim 7 (depends on 1)

The track-and-hold circuit of claim 1, wherein the discrete-time amplifier is a closed-loop amplifier.

### Claim 8 (depends on 1)

The track-and-hold circuit of claim 1, further comprising a second matching network that is to match an impedance of the balun to an impedance of the second buffer.

### Claim 9

A track-and-hold circuit comprising:
a balun that is to receive a single-ended input signal and output a differential output signal at a first output and a second output of the balun based on the single-ended input signal;
a first sampling network with dither injection coupled with the first output of the balun;
a second sampling network with dither injection coupled with the second output of the balun;
a first matching circuit that is to match an impedance of the balun with an impedance of the first sampling network; and
a second matching circuit that is to match an impedance of the balun with an impedance of the second sampling network.

### Claim 10 (depends on 9)

The track-and-hold circuit of claim 9, wherein the balun is to effectively output a single-ended output signal if a frequency of the single-ended input signal is below a threshold frequency.

### Claim 11 (depends on 10)

The track-and-hold circuit of claim 10, wherein the threshold frequency is below 2 gigahertz (GHz).

### Claim 12 (depends on 9)

The track-and-hold circuit of claim 9, wherein the balun is to output the differential output signal if a frequency of the single-ended input signal is above a threshold frequency.

### Claim 13 (depends on 12)

The track-and-hold circuit of claim 12, wherein the threshold frequency is 8 gigahertz (GHz).

### Claim 14 (depends on 9)

The track-and-hold circuit of claim 9, wherein the first matching circuit includes a resistor with a value that is based on a low-frequency impedance match of the balun.

### Claim 15 (depends on 9)

The track-and-hold circuit of claim 9, wherein the first matching circuit includes a capacitor with a value that is based on a transition frequency of the balun.

### Claim 16

A method, comprising:
converting a single-ended input signal to a differential output signal at a first and second outputs;
sampling, by a first sampling network, the first output;
sampling, by a second sampling network, the second output;
randomly changing a polarity of a differential signal sampled by the first sampling network and the second sampling network; and
amplifying, by a discrete-time amplifier, the differential signal.

### Claim 17 (depends on 16)

The method of claim 16, wherein converting the single-ended input signal to the differential output signal comprises:
effectively outputting a single-ended output signal if a frequency of the single-ended input signal is below a threshold frequency.

### Claim 18 (depends on 16)

The method of claim 16, wherein converting the single-ended input signal to the differential output signal comprises:
outputting the differential output signal if a frequency of the single-ended input signal is above a threshold frequency.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
injecting an additive dither in one or more of: the first sampling network and the second sampling network; and
calibrating the discrete-time amplifier based on the additive dither.

### Claim 20 (depends on 16)

The method of claim 16, wherein randomly changing the polarity of the differential signal randomizes even-order distortion of the discrete-time amplifier.