# US 10,873,335 B2 · Divider control and reset for phase-locked loops

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- Number: US 10,873,335 B2
- Document ID: US10873335B2
- Status: Granted
- Kind: B2
- Application number: 16/401,737
- Filed: 2019-05-02
- Published: 2020-11-05
- Granted: 2020-12-22
- Earliest claimed: 2019-05-02
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Cristian Marcu; Feng Zhao; Wei Deng; Chunwei Chang; Robert K. Kong; Saeed Chehrazi
- Web page: https://patentgrep.com/patent/US10873335B2

## CPC

- H03L 7/113: using frequency discriminator
- H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence)
- H03K 21/38: Starting, stopping or resetting the counter (counters with a base other than a power of two H03K23/48, H03K23/66)
- H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump}
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/183: a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number {(H03L7/1806 takes precedence)}
- H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.

## Claims

### Claim 1

An apparatus, comprising:
a phase-locked loop circuit including a programmable divider circuit that includes a plurality of divider stages, wherein the phase-locked loop circuit is configured to generate a clock signal using a reference signal; and
a divider control circuit that includes a plurality of flip-flop circuits, wherein the divider control circuit is configured, in response to an initiation of a frequency calibration operation being performed on the phase-locked loop circuit, to:
generate a timing signal using respective output signals of at least two divider stages of the plurality of divider stages, wherein the timing signal is generated in response to a determination that one or more of the plurality of divider stages have reached a particular logic state during the frequency calibration operation; and
toggle, using the timing signal, at least one of the plurality of flip-flop circuits to generate a pause signal; and
wherein the programmable divider circuit is configured to hold the particular logic state of the one or more of the plurality of divider stages using the pause signal.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the phase-locked loop circuit further includes an oscillator circuit, a phase detector circuit, a charge pump circuit, and a filter circuit, and wherein the divider control circuit is further configured, in response to the initiation of the frequency calibration operation, to disable the phase detector circuit, the charge pump circuit, and the filter circuit.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the divider control circuit is further configured to:
in response to completion of the frequency calibration operation and in response to a detection of a particular phase relationship between the reference signal and an output programmable divider circuit, enable the phase detector circuit.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the divider control circuit is further configured to, enable the charge pump circuit and the filter circuit, in response to the detection that the particular phase relationship.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein a particular divider stage of the plurality of divider stages is configured to selectively divide, based on a program data bit, a frequency of an input signal.

### Claim 6

A method, comprising:
initiating a frequency calibration operation for a phase-locked loop circuit that includes a programmable divider circuit comprising a plurality of divider stages;
in response to initiating the frequency calibration operation:
generating, by a divider control circuit comprising a plurality of flip-flop circuits, a timing signal based on respective output signals of at least two divider stages of the plurality of divider stages, wherein the timing signal is generated in response to determining that one or more divider stages of the plurality of divider stages have reached a particular logic state; and
toggling at least one of the plurality of flip-flop circuits using the timing signal to generate a pause signal;
maintaining the particular logic state by holding the one or more divider stages using the pause signal; and
releasing the one or more divider stages from the particular logic state upon completing the frequency calibration operation.

### Claim 7 (depends on 6)

The method of claim 6, further comprising in response to initiating the frequency calibration operation, opening a feedback loop of the phase-locked loop circuit.

### Claim 8 (depends on 7)

The method of claim 7, wherein the phase-locked loop circuit includes a phase detector circuit, a charge pump circuit, and a filter circuit included in the phase-locked loop circuit, and wherein opening the feedback loop includes disabling the phase detector circuit, the charge pump circuit, and the filter circuit.

### Claim 9 (depends on 8)

The method of claim 8, further comprising, upon completion of the frequency calibration operation, enabling the phase detector circuit, the charge pump circuit, and the filter circuit based on a phase relationship between a reference signal and an output signal of the programmable divider circuit.

### Claim 10 (depends on 6)

The method of claim 6, further comprising disabling the pause signal in response to receiving a reset signal.

### Claim 11 (depends on 6)

The method of claim 6, further comprising setting respective control signals for the one or divider stages to change a divisor of the programmable divider circuit.

### Claim 12

An apparatus, comprising:
an oscillator circuit configured to generate an oscillator signal, wherein a frequency of the oscillator signal is based on a voltage level of a control signal;
a programmable divider circuit including a plurality of divider stages, wherein the programmable divider circuit is configured to generate a divided signal using the oscillator signal, wherein a frequency of the divided signal is less than the frequency of the oscillator signal, wherein a given one of the plurality of divider stages is configured to change a frequency divisor in response to a control signal;
a phase detector circuit configured to compare a reference signal and the divided signal;
a charge pump circuit configured to modify, based on a result of a comparison of the reference signal and the divided signal, the voltage level of the control signal;
a control circuit configured to:
during a frequency calibration operation:
deactivate the programmable divider circuit, the phase detector circuit, and the charge pump circuit; and
hold one or more divider stages of the plurality of divider stages in a particular logic state; and
in response to a completion of the frequency calibration operation, reactivate the programmable divider circuit, phase detector circuit, and the charge pump circuit based on a comparison of respective phases of the reference signal and the divided signal.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein to hold the one or more divider stages of the plurality of divider stages in the particular logic state, the control circuit is further configured to generate a timing signal using respective output signals of at least two divider stages of the plurality of divider stages.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the control circuit is further configured to generate a delayed version of the timing signal by toggling at least one flip-flop circuit using the timing signal.

### Claim 15 (depends on 12)

The apparatus of claim 12, wherein the programmable divider circuit is further configured to generate a clock signal using the oscillator signal, wherein a different frequency of the clock signal is less than the frequency of the oscillator signal and different than the frequency of the divided signal.

### Claim 16 (depends on 12)

The apparatus of claim 12, wherein the control circuit is further configured, during the frequency calibration operation, adjust the frequency of the oscillator signal by adjusting operation of the oscillator circuit.