# US 10,873,333 B2 · Spur frequency estimation inside digital phase locked loop

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- Number: US 10,873,333 B2
- Document ID: US10873333B2
- Status: Granted
- Kind: B2
- Application number: 16/609,280
- Filed: 2017-05-31
- Published: 2020-06-18
- Granted: 2020-12-22
- Earliest claimed: 2017-05-31
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Rotem Avivi; Michael Kerner; Yair Dgani
- Web page: https://patentgrep.com/patent/US10873333B2

## CPC

- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L 2207/50: All digital phase-locked loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

Systems and methods configured to cancel spurs in a phase locked loop (PLL) system are provided. A method configured to cancel spurs in a PLL system includes receiving a PLL signal from the PLL system; determining an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal; and canceling the spur in the received PLL signal based on the estimated spur frequency.

## Claims

### Claim 1

A frequency generation system, comprising:
a spur frequency estimation circuitry configured to:
receive a phase locked loop (PLL) signal from a PLL;
determine an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal; and
an inverse spur circuitry configured to cancel the spur in the received PLL signal based on the estimated spur frequency.

### Claim 2 (depends on 1)

The frequency generation system of claim 1, wherein the received PLL signal comprises a phase error signal generated by a phase detector of the PLL.

### Claim 3 (depends on 1)

The frequency generation system of claim 1, wherein the spur frequency estimation circuitry comprises a processing circuitry configured to:
analyze a Fourier transform (FT) of the received PLL signal;
determine a frequency at which the FT of the received PLL signal exceeds a threshold; and
determine the estimated spur frequency as the frequency at which the FT of the received PLL signal exceeds the threshold.

### Claim 4 (depends on 1)

The frequency generation system of claim 1, wherein the spur frequency estimation circuitry comprises a processing circuitry configured to apply a parametric algorithm to determine the estimated spur frequency.

### Claim 5 (depends on 1)

The frequency generation system of claim 1, wherein the received PLL signal is a digital signal.

### Claim 6 (depends on 1)

The frequency generation system of claim 1, wherein:
the inverse spur circuitry is configured to generate an inverse spur signal based on the estimated spur frequency; and
the frequency generation system comprises an injection circuitry configured to inject the inverse spur signal into the PLL to cancel the spur in the PLL signal.

### Claim 7 (depends on 6)

The frequency generation system of claim 6, wherein the injection circuitry is configured to select a first inverse spur signal path or a second inverse spur signal path based on a selection input, wherein the injection circuitry comprises:
a first adder element connected to the first inverse spur signal path and disposed at an input to a phase detector of the PLL; and
a second adder element connected to the second inverse spur signal path and disposed at an output of a lowpass filter of the PLL.

### Claim 8

A method configured to cancel spurs in a phase locked loop (PLL) system, comprising:
receiving a PLL signal from the PLL system;
determining an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal; and
canceling the spur in the received PLL signal based on the estimated spur frequency.

### Claim 9 (depends on 8)

The method of claim 8, wherein the receiving comprises receiving a phase error signal generated by a phase detector of the PLL.

### Claim 10 (depends on 8)

The method of claim 8, wherein the determining comprises:
analyzing a Fourier transform (FT) of the received PLL signal;
determining a frequency at which the FT of the received PLL signal exceeds a threshold; and
determining the estimated spur frequency as the frequency at which the FT of the received PLL signal exceeds the threshold.

### Claim 11 (depends on 10)

The method of claim 10, comprising utilizing a parametric algorithm to determine the estimated spur frequency.

### Claim 12 (depends on 8)

The method of claim 8, wherein the received PLL signal is a digital signal.

### Claim 13 (depends on 8)

The method of claim 8, further comprising:
generating an inverse spur signal based on the estimated spur frequency; and
injecting the inverse spur signal into the PLL to cancel the spur in the PLL signal.

### Claim 14 (depends on 13)

The method of claim 13, comprising:
selecting a first inverse spur signal path or a second inverse spur signal path based on a selection input; and
if the first inverse spur signal path is selected, injecting the inverse spur signal at an input to a phase detector of the PLL; and
if the second inverse spur signal path is selected, injecting the inverse spur signal at an output of a lowpass filter of the PLL.

### Claim 15

A spur frequency estimation circuitry, comprising:
an input circuitry configured to receive a phase locked loop (PLL) signal from a PLL; and
a processing circuitry configured to determine an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal.

### Claim 16 (depends on 15)

The spur frequency estimation circuitry of claim 15, wherein the received PLL signal comprises a phase error signal generated by a phase detector of the PLL.

### Claim 17 (depends on 15)

The spur frequency estimation circuitry of claim 15, wherein the processing circuitry is configured to:
analyze a Fourier transform (FT) of the received PLL signal;
determine a frequency at which the FT of the received PLL signal exceeds a threshold; and
determine the estimated spur frequency as the frequency at which the FT of the received PLL signal exceeds the threshold.

### Claim 18 (depends on 15)

The spur frequency estimation circuitry of claim 15, wherein the processing circuitry is configured to apply a parametric algorithm to determine the estimated spur frequency.

### Claim 19

A computer-readable storage device storing computer-executable instructions that, in response to execution by a processor, cause the processor to cancel spurs in a phase locked loop (PLL) system, wherein the instructions include instructions for:
receiving a PLL signal from the PLL system;
determining an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal; and
canceling the spur in the received PLL signal based on the estimated spur frequency.

### Claim 20 (depends on 19)

The computer-readable storage device of claim 19, wherein the instructions for receiving comprise instructions for receiving a phase error signal generated by a phase detector of the PLL.

### Claim 21 (depends on 19)

The computer-readable storage device of claim 19, wherein the instructions for determining comprise instructions for:
analyzing a Fourier transform (FT) of the received PLL signal;
determining a frequency at which the FT of the received PLL signal exceeds a threshold; and
determining the estimated spur frequency as the frequency at which the FT of the received PLL signal exceeds the threshold.

### Claim 22 (depends on 19)

The computer-readable storage device of claim 19, wherein the instructions for determining comprise instructions for utilizing a parametric algorithm to determine the estimated spur frequency.