# US 10,873,331 B2 · Clamp logic circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,873,331 B2
- Document ID: US10873331B2
- Status: Granted
- Kind: B2
- Application number: 16/102,685
- Filed: 2018-08-13
- Published: 2019-02-28
- Granted: 2020-12-22
- Earliest claimed: 2017-08-25
- Assignees: RichWave Technology Corp.
- Applicants: RichWave Technology Corp.
- Inventors: Chih-Sheng Chen; Tien-Yun Peng
- Web page: https://patentgrep.com/patent/US10873331B2

## CPC

- H03K 19/09403: {using junction field-effect transistors (H03K19/096 takes precedence)}
- H02H 9/02: responsive to excess current {(current limitation for voltage regulators G05F1/573; disconnection after limiting H02H3/025)}
- H02H 9/025: {Current limitation using field effect transistors}
- H03H 17/0248: {Filters characterised by a particular frequency response or filtering method}
- H03K 19/0175: Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00)
- H03K 19/09429: {one of the states being the high impedance or floating state}
- H03K 19/1733: {Controllable logic circuits (H03K19/177 takes precedence)}
- H03K 2217/0036: Means reducing energy consumption
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

A clamp logic circuit has a logic circuit, a control terminal, a current clamp circuit and an output terminal. The logic circuit has at least a junction field-effect transistor (JFET). The control terminal receives an input signal. The current clamp circuit has a transistor and a resistor. A first end of the transistor is coupled to the control terminal, a second end of the transistor is coupled to a first end of the resistor, a control end of the transistor is coupled to a reference voltage, and a second end of the resistor is coupled to an input end of the logic circuit. The output terminal is coupled to an output end of the logic circuit.

## Claims

### Claim 1

A clamp logic circuit, comprising:
a logic circuit, comprising at least a junction field-effect transistor (JFET);
a control terminal, configured to receive an input signal;
a current clamp circuit, configured to limit a maximum of a current flowing from the control terminal into the current clamp circuit to be less than a predetermined value when an external alternating current (AC) signal is transmitted to the control terminal, the current clamp circuit comprising a first transistor and a first resistor, a first end of the first transistor being coupled to the control terminal, a second end of the first transistor being coupled to a first end of the first resistor, a control end of the first transistor being coupled to a reference voltage, and a second end of the first resistor being coupled to an input end of the logic circuit; and
an output terminal, coupled to an output end of the logic circuit.

### Claim 2 (depends on 1)

The clamp logic circuit of claim 1, wherein the current clamp circuit further comprises a high impedance network coupled between the control end of the first transistor and the reference voltage, and the high impedance network comprises a resistor, a transistor or an inductor.

### Claim 3 (depends on 1)

The clamp logic circuit of claim 1, wherein the logic circuit comprises an inverter.

### Claim 4 (depends on 1)

The clamp logic circuit of claim 1, wherein the at least a JFET comprises a plurality of JFETs, and the plurality of JFETs are a plurality of pseudomorphic high-electron-mobility transistors (pHEMTs).

### Claim 5 (depends on 1)

The clamp logic circuit of claim 1, wherein the first transistor is a depletion-mode (D-mode) field-effect transistor (FET).

### Claim 6 (depends on 2)

The clamp logic circuit of claim 2 further comprising a first capacitor, a first end of the first capacitor being coupled to the input end of the logic circuit and the second end of the first resistor, a second end of the first capacitor being coupled to the reference voltage, and the first capacitor and the first resistor forming a low pass filter.

### Claim 7 (depends on 3)

The clamp logic circuit of claim 3, wherein the at least a JFET comprises an enhancement-mode (E-mode) field-effect transistor (FET) and a depletion-mode (D-mode) field-effect transistor (FET).

### Claim 8 (depends on 6)

The clamp logic circuit of claim 6 further comprising a direct current (DC) offset circuit coupled between the control terminal and the first end of the first transistor.

### Claim 9 (depends on 8)

The clamp logic circuit of claim 8, wherein the DC offset circuit comprises a first rectifying device, a first end of the first rectifying device is coupled to the control terminal, and a second end of the first rectifying device is coupled to the first end of the first transistor.

### Claim 10 (depends on 8)

The clamp logic circuit of claim 8 further comprising a low pass filter coupled between the control terminal and the DC offset circuit.

### Claim 11 (depends on 9)

The clamp logic circuit of claim 9, wherein the first rectifying device comprises a diode-connected transistor, a first end and a control end of the diode-connected transistor are coupled to each other and are coupled to the control terminal, and a second end of the diode-connected transistor is coupled to the first end of the first transistor.

### Claim 12 (depends on 9)

The clamp logic circuit of claim 9, wherein the first rectifying device comprises a first diode, a first end of the first diode is coupled to the control terminal, and a second end of the first diode is coupled to the first end of the first transistor.

### Claim 13 (depends on 9)

The clamp logic circuit of claim 9 further comprising a second rectifying device, a first end of the second rectifying device being coupled to the second end of the first rectifying device, and a second end of the second rectifying device being coupled to the first end of the first rectifying device, wherein the second rectifying device and the first rectifying device provide a bi-directional conducting path between the control terminal of the clamp logic circuit and the first end of the first transistor.

### Claim 14 (depends on 11)

The clamp logic circuit of claim 11 further comprising at least one of a first high pass filter, a second high pass filter and a third high pass filter, wherein the first high pass filter is coupled between the first end of the first transistor and the second end of the first transistor, the second high pass filter is coupled between the first end of the diode-connected transistor and the second end of the diode-connected transistor, and the third high pass filter is coupled between the control end of the first transistor and the control end of the diode-connected transistor.

### Claim 15 (depends on 11)

The clamp logic circuit of claim 11 further comprising at least one of a first high pass filter and a second high pass filter, wherein the first high pass filter is coupled between the control terminal of the clamp logic circuit and the second end of the first transistor, and the second high pass filter is coupled between the control end of the first transistor and the control end of the diode-connected transistor.

### Claim 16 (depends on 12)

The clamp logic circuit of claim 12 further comprising a second rectifying device, wherein the second rectifying device comprises a second diode, a first end of the second diode is coupled to the second end of the first diode, and a second end of the second diode is coupled to the first end of the first diode.

### Claim 17 (depends on 13)

The clamp logic circuit of claim 13 further comprising a first high pass filter, wherein the first high pass filter is coupled between the control end of the first transistor and the second end of the first rectifying device.

### Claim 18 (depends on 14)

The clamp logic circuit of claim 14, wherein the first high pass filter comprises a second capacitor, the second high pass filter comprises a third capacitor or the third high pass filter comprises a fourth capacitor.

### Claim 19 (depends on 15)

The clamp logic circuit of claim 15, wherein the first high pass filter comprises a second capacitor or the second high pass filter comprises a third capacitor.

### Claim 20 (depends on 17)

The clamp logic circuit of claim 17, wherein the first high pass filter comprises a second capacitor.