# US 10,873,325 B2 · Robust noise immune, low-skew, pulse width retainable glitch-filter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,873,325 B2 - Document ID: US10873325B2 - Status: Granted - Kind: B2 - Application number: 16/531,180 - Filed: 2019-08-05 - Published: 2020-04-16 - Granted: 2020-12-22 - Earliest claimed: 2018-10-12 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Jhankar Malakar; Srikanth Srinivasan; Devraj Matharampallil Rajagopal - Web page: https://patentgrep.com/patent/US10873325B2 ## CPC - H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) - H03K 17/04163: {in field-effect transistor switches} - H03K 17/6872: {using complementary field-effect transistors} - H03K 2005/00019: {Variable delay} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switches to the feedback switches to accelerate the pull up or the pull down. ## Claims ### Claim 1 A glitch filter comprising; a first set of CMOS transistors; a first resistor-capacitor (RC) filter coupled to the first set of CMOS transistors; a second set of CMOS transistors coupled to the first RC filter; a second RC filter coupled to the second set of CMOS transistors; and an output inverter coupled to the second RC filter, wherein the first set of CMOS transistors is configured to apply high or low voltage to the first RC filter based on an input signal provided to the glitch filter; the first RC filter is configured to generate output voltage based on the high or low voltage applied to the first RC filter by the first set of CMOS transistors; the second set of CMOS transistors is configured to apply high or low voltage to the second RC filter based on the output voltage generated by the first RC filter; the second RC filter is configured to generate an output signal corresponding to the input signal provided to the first set of CMOS transistors based on the high or low voltage applied to the second RC filter by the second set of CMOS transistors, and the output inverter is configured to delay a rising edge or a falling edge of the output signal to compensate a signal skew based on the first set of CMOS transistors or the second set of CMOS transistors. ### Claim 2 (depends on 1) The glitch filter of claim 1 further comprising, a first set of feedback switches coupled to the first RC filter; wherein the first set of feedback switches is configured to pull up or pull down the output voltage of the first RC filter based on the output signal generated by the second RC filter. ### Claim 3 (depends on 2) The glitch filter of claim 2, wherein the glitch filter further comprises a feedback inverter coupled to the output inverter, and configured to output a first feedback signal based on an output of the output inverter and bias the first set of feedback switches, wherein the first set of feedback switches comprises, a first feedback PMOS transistor of which a drain is coupled to an output voltage node of the first RC filter, a source is coupled to a high voltage supply, and a gate is coupled to an output of the feedback inverter, and a first feedback NMOS transistor of which a drain is coupled to the output voltage node of the first RC filter, a source is coupled to a low voltage supply and a gate is coupled to the output of the feedback inverter, and wherein the first feedback PMOS transistor is configured to be turned on to pull up the voltage of the output voltage node to a voltage of the high voltage supply when the first feedback signal output from the feedback inverter is low, and the first feedback NMOS transistor is configured to be turned on to pull down the voltage of the output voltage node to a voltage of the low voltage supply when the first feedback signal output from the feedback inverter is high. ### Claim 4 (depends on 2) The glitch filter of claim 2 further comprising, a first set of input biased switches coupled to the first set of feedback switches, wherein the first set of input biased switches is configured to revert the output voltage of the first RC filter to a previous rail when a pulse width of the input signal provided to the glitch filter is shorter than a preset pulse width. ### Claim 5 (depends on 4) The glitch filter of claim 4, wherein the glitch filter further comprises an input inverter coupled to the first set of CMOS transistors, and configured to output an inverted input signal based on the input signal and bias the first set of input biased switches, wherein the first set of input biased switches comprises, a first input PMOS transistor of which a source is coupled to a high voltage supply, a drain is coupled to a first feedback switch of the first set of feedback switches, and a gate is coupled to an output of the input inverter, and a first input NMOS transistor of which a source is coupled to a low voltage supply, a drain is coupled to a second feedback switch of the first set of feedback switches, and a gate is coupled to the output of the input inverter, and wherein the first input PMOS transistor is configured to be turned on when the inverted input signal from the input inverter is low, and the first input NMOS transistor is configured to be turned on when the inverted input signal from the input inverter is high. ### Claim 6 (depends on 1) The glitch filter of claim 1 further comprising, a second set of feedback switches coupled to the second RC filter; wherein the second set of feedback switches is configured to pull up or pull down a voltage of the output signal of the second RC filter based on the output signal generated by the second RC filter. ### Claim 7 (depends on 6) The glitch filter of claim 6, wherein the second set of feedback switches comprises, a second feedback PMOS transistor of which a drain is coupled to an output signal node of the second RC filter, a source is coupled to a high voltage supply, and a gate is coupled to an output of the output inverter, and a second feedback NMOS transistor of which a drain is coupled to the output signal node of the second RC filter, a source is coupled to a low voltage supply and a gate is coupled to the output of the output inverter, and wherein the output inverter is configured to output a second feedback signal to bias the second feedback PMOS and NMOS transistors based on the output signal of the second RC filter, the second feedback PMOS transistor is configured to be turned on to pull up the voltage of the output signal node to a voltage of the high voltage supply when the second feedback signal output from the output inverter is low, and the second feedback NMOS transistor is configured to be turned on to pull down a voltage of the output signal node to a voltage of the low voltage supply when the second feedback signal output from the output inverter is high. ### Claim 8 (depends on 6) The glitch filter of claim 6 further comprising, a second set of input biased switches coupled to the second RC filter, wherein the second set of input biased switches are configured to revert the voltage of the output signal of the second RC filter to a previous rail when a pulse width of the input signal provided to the glitch filter is shorter than a preset pulse width. ### Claim 9 (depends on 8) The glitch filter of claim 8, wherein the second set of input biased switches comprises, a second input PMOS transistor of which a source is coupled to a high voltage supply, a drain is coupled to a first feedback switch of the second set of feedback switches, and a gate is configured to be biased by the input signal, and a second input NMOS transistor of which a source is coupled to a low voltage supply, a drain is coupled to a second feedback switch of the second set of feedback switches, and a gate is configured to be biased by the input signal, and wherein the second input PMOS transistor is configured to be turned on when the input signal is low, and the second input NMOS transistor is configured to be turned on when the input signal is high. ### Claim 10 (depends on 6) The glitch filter of claim 6 further comprising, a set of feedforward switches coupled to the second set of feedback switches, wherein each switch of the set of feedforward switches is coupled to a respective switch of the second set of feedback switches, and the each switch of the set of feedforward switches is configured to be turned on or turned off before the respective switch of the second set of feedback switches is turned on or turned off. ### Claim 11 (depends on 10) The glitch filter of claim 10, wherein the glitch filter further comprises a delay logic coupled to an output voltage node of the first RC filter, and configured to output a feedforward signal based on a delayed output voltage of the first RC filter and bias the set of feedforward switches, wherein the set of feedforward switches comprises, a feedforward PMOS transistor of which a source is coupled to a high voltage supply, a drain is coupled to a first feedback switch of the second set of feedback switches, and a gate is coupled to an output of the delay logic, and a feedforward NMOS transistor of which a source is coupled to a low voltage supply, a drain is coupled to a second feedback switch of the second set of feedback switches, and a gate is coupled to the output of the delay logic, and wherein the feedforward PMOS transistor is configured to be turned on when the feedforward signal from the delay logic is low, and the feedforward NMOS transistor is configured to be turned on when the feedforward signal from the delay logic is high. ### Claim 12 (depends on 11) The glitch filter of claim 11, wherein the delay logic is configured to generate the feedforward signal to turn on and turn off the feedforward PMOS transistor before the first feedback switch of the second set of feedback switches is turned on and turned off, respectively, and to turn on and turn off the feedforward NMOS transistor before the second feedback switch of the second set of feedback switches is turned on and turned off, respectively. ### Claim 13 (depends on 11) The glitch filter of claim 11, wherein the delay logic comprises two inverters coupled in series. ### Claim 14 A glitch filter comprising; a set of CMOS transistors; a resistor-capacitor (RC) filter coupled to the set of CMOS transistors; an output inverter coupled to the RC filter; a set of feedback switches coupled to the RC filter and the output inverter; and a set of feedforward switches coupled to the feedback switches, wherein the set of CMOS transistors is configured to apply high or low voltage to the RC filter based on an input signal provided to the glitch filter; the RC filter is configured to generate an output signal based on the high or low voltage applied to the RC filter by the set of CMOS transistor; and the output inverter is configured to invert the output signal and provide the inverted output signal to the set of feedback switches; the set of feedback switches is configured to pull up or pull down a voltage of the output signal based on the inverted output signal; and the set of the feedforward switches is configured to accelerate the pull up or pull down of the voltage by the set of feedback switches based on a delayed input signal. ### Claim 15 (depends on 14) The glitch filter of claim 14, wherein the set of feedback switches comprises a feedback PMOS transistor and a feedback NMOS transistor, and the set of feedforward switches comprises a feedforward PMOS transistor and a feedforward NMOS transistor, wherein a drain of the feedback PMOS transistor is coupled to an output signal node of the RC filter, a source of the feedback PMOS transistor is coupled to the feedforward PMOS transistor, and a gate of the feedback PMOS transistor is configured to be biased by the inverted output signal, a drain of the feedback NMOS transistor is coupled to the output signal node of the RC filter, a source of the feedback NMOS transistor is coupled to the feedforward NMOS transistor, and a gate of the feedback NMOS transistor is configured to be biased by the inverted output signal, a source of the feedforward PMOS transistor is coupled to a high voltage supply, a drain of the feedforward PMOS transistor is coupled to the source of the feedback PMOS transistor, and a gate of the feedforward PMOS transistor is configured to be biased by the delayed input signal, and a source of the feedforward NMOS transistor is coupled to a low voltage supply, a drain of the feedforward NMOS transistor is coupled to the source of the feedback NMOS transistor, and a gate of the feedforward NMOS transistor is configured to be biased by the delayed input signal. ### Claim 16 (depends on 15) The glitch filter of claim 15, wherein a rising and falling edge of the delayed input signal is configured to precede a respectively corresponding rising and falling edge of the inverted output signal. ### Claim 17 (depends on 15) The glitch filter of claim 15 further comprising; a set of input biased switches coupled to the feedback switches, wherein the set of the input biased switches is configured to revert the voltage of the output signal to a previous rail when a pulse width of the input signal is shorter than a preset pulse width. ### Claim 18 (depends on 17) The glitch filter of claim 17, wherein the set of input biased switches comprises an input biased PMOS transistor and an input biased NMOS transistor, a source of the input biased PMOS transistor is coupled to the high voltage supply, a drain of the input biased PMOS transistor is coupled to the source of the feedback PMOS transistor, and a gate of the input biased PMOS transistor is configured to be biased by the input signal, and a source of the input biased NMOS transistor is coupled to the low voltage supply, a drain of the input biased NMOS transistor is coupled to the source of the feedback NMOS transistor, and a gate of the input biased NMOS transistor is configured to be biased by the input signal. ### Claim 19 (depends on 18) The glitch filter of claim 18, wherein a rising and falling edge of the input signal is configured to bias the input biased PMOS and NMOS transistors before a respectively corresponding rising and falling edge of the delayed input signal bias the feedforward PMOS and NMOS transistors.