# US 10,873,324 B2 · Pulse stretcher circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,873,324 B2 - Document ID: US10873324B2 - Status: Granted - Kind: B2 - Application number: 16/026,946 - Filed: 2018-07-03 - Published: 2020-01-09 - Granted: 2020-12-22 - Earliest claimed: 2018-07-03 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Shri Sagar Dwivedi; Fakhruddin Ali Bohra; Lalit Gupta; Yew Keong Chong; Gus Yeung - Web page: https://patentgrep.com/patent/US10873324B2 ## CPC - H03K 5/06: by the use of delay lines or other analogue delay elements - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width. ## Claims ### Claim 1 An integrated circuit, comprising: clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width; first pulse stretching circuitry coupled between the clock generation circuitry and input latch control circuitry, wherein the first pulse stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal, and wherein the second clock signal has a second pulse width that is at least greater than the first pulse width; and second pulse stretching circuitry coupled between the clock generation circuitry and read-write circuitry, wherein the second pulse stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal, and wherein the third clock signal has a third pulse width that is at least greater than the first pulse width; wherein the read-write circuitry comprises input data circuitry, write enable pin circuitry and latch circuitry. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the second pulse width has a delayed falling edge and a delayed opening edge of a latch clock. ### Claim 3 An integrated circuit, comprising: clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width; first pulse stretching circuitry coupled between the clock generation circuitry and input latch control circuitry, wherein the first pulse stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal, and wherein the second clock signal has a second pulse width that is at least greater than the first pulse width; and second pulse stretching circuitry coupled between the clock generation circuitry and read-write circuitry, wherein the second pulse stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal, and wherein the third clock signal has a third pulse width that is at least greater than the first pulse width; wherein the first clock signal comprises a first global timing pulse signal, and wherein the clock generation circuitry provides the first global timing pulse signal to the first pulse stretching circuitry and the second pulse stretching circuitry; wherein the clock generation circuitry provides a second global timing pulse signal to the first pulse stretching circuitry and the second pulse stretching circuitry, and wherein the second global timing pulse signal is a complement of the first global timing pulse signal; wherein the first pulse stretching circuitry receives the first global timing pulse signal and the second global timing pulse signal and provides the second clock signal to the input latch control circuitry based on the enable signal. ### Claim 4 An integrated circuit, comprising: clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width; first pulse stretching circuitry coupled between the clock generation circuitry and input latch control circuitry, wherein the first pulse stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal, and wherein the second clock signal has a second pulse width that is at least greater than the first pulse width; and second pulse stretching circuitry coupled between the clock generation circuitry and read-write circuitry, wherein the second pulse stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal, and wherein the third clock signal has a third pulse width that is at least greater than the first pulse width; wherein the first clock signal comprises a first global timing pulse signal, and wherein the clock generation circuitry provides the first global timing pulse signal to the first pulse stretching circuitry and the second pulse stretching circuitry; wherein the clock generation circuitry provides a second global timing pulse signal to the first pulse stretching circuitry and the second pulse stretching circuitry, and wherein the second global timing pulse signal is a complement of the first global timing pulse signal; wherein the first pulse stretching circuitry comprises multiple first logic devices that are arranged to receive the first global timing pulse signal and the second global timing pulse signal and to provide the second clock signal to the input latch control circuitry based on the enable signal. ### Claim 5 (depends on 4) The integrated circuit of claim 4, wherein the first pulse stretching circuitry further comprises first resistor-capacitor (RC) circuitry that receives the first global timing pulse, delays the first global timing pulse, and provides a delayed first global timing pulse to a first multiplexer of the multiple first logic devices, and wherein the first multiplexer provides a first intermediate global timing pulse to one or more other logic devices of the multiple first logic devices based on the enable signal. ### Claim 6 (depends on 5) The integrated circuit of claim 5, wherein the one or more other logic devices of the multiple first logic devices are arranged to receive the second global timing pulse and the first intermediate global timing pulse and provide the second clock signal to the input latch control circuitry. ### Claim 7 An integrated circuit, comprising: clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width; first pulse stretching circuitry coupled between the clock generation circuitry and input latch control circuitry, wherein the first pulse stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal, and wherein the second clock signal has a second pulse width that is at least greater than the first pulse width; and second pulse stretching circuitry coupled between the clock generation circuitry and read-write circuitry, wherein the second pulse stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal, and wherein the third clock signal has a third pulse width that is at least greater than the first pulse width; wherein the first clock signal comprises a first global timing pulse signal, and wherein the clock generation circuitry provides the first global timing pulse signal to the first pulse stretching circuitry and the second pulse stretching circuitry; wherein the clock generation circuitry provides a second global timing pulse signal to the first pulse stretching circuitry and the second pulse stretching circuitry, and wherein the second global timing pulse signal is a complement of the first global timing pulse signal; and wherein the second pulse stretching circuitry receives the first global timing pulse signal, the second global timing pulse signal, and a write enable signal and provides the third clock signal to the read-write circuitry based on the enable signal, and wherein the second pulse stretching circuitry receives the write enable signal from the input latch control circuitry. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein the second pulse stretching circuitry comprises multiple second logic devices that are arranged to receive the first global timing pulse signal, the second global timing pulse signal, and the write enable signal and provide the third clock signal to the read-write circuitry based on the enable signal. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein the second pulse stretching circuitry further comprises second resistor-capacitor (RC) circuitry that receives the first global timing pulse, delays the first global timing pulse, and provides a delayed first global timing pulse to a second multiplexer of the multiple second logic devices, and wherein the second multiplexer provides a second intermediate global timing pulse to one or more other logic devices of the multiple second logic devices based on the enable signal. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein the one or more other logic devices of the multiple second logic devices are arranged to receive the second global timing pulse, write enable signal, and the first intermediate global timing pulse and provide the third clock signal to the read-write circuitry. ### Claim 11 An integrated circuit, comprising: clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width; first pulse stretching circuitry coupled between the clock generation circuitry and input latch control circuitry, wherein the first pulse stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal, and wherein the second clock signal has a second pulse width that is at least greater than the first pulse width; and second pulse stretching circuitry coupled between the clock generation circuitry and read-write circuitry, wherein the second pulse stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal, and wherein the third clock signal has a third pulse width that is at least greater than the first pulse width; wherein the read-write circuitry comprises a column multiplexer along with a write driver for write operations and a sense amplifier for read operations, and wherein the read-write circuitry is used for fixing an external hold margin with the enable signal as an external control signal. ### Claim 12 An integrated circuit, comprising: clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width; first pulse stretching circuitry coupled between the clock generation circuitry and input latch control circuitry, wherein the first pulse stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal, and wherein the second clock signal has a second pulse width that is at least greater than the first pulse width; second pulse stretching circuitry coupled between the clock generation circuitry and read-write circuitry, wherein the second pulse stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal, and wherein the third clock signal has a third pulse width that is at least greater than the first pulse width; and dummy bitline circuitry having control logic coupled between a dummy bitline and a reset signal line, wherein the clock generation circuitry provides a reset signal to the control logic via the reset signal line. ### Claim 13 A method, comprising: fabricating clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width; fabricating first pulse stretching circuitry coupled between the clock generation circuitry and input latch control circuitry, wherein the first pulse stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on a enable signal, and wherein the second clock signal has a second pulse width that is at least greater than the first pulse width; fabricating second pulse stretching circuitry coupled between the clock generation circuitry and read-write circuitry, wherein the second pulse stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal, and wherein the third clock signal has a third pulse width that is at least greater than the first pulse width; and fabricating dummy bitline circuitry having control logic coupled between a dummy bitline and a reset signal line, wherein the clock generation circuitry provides a reset signal to the control logic via the reset signal line. ### Claim 14 (depends on 1) The integrated circuit of claim 1, wherein the input latch control circuitry comprises one or more first latches, wherein each of the one or more first latches is configured to receive multiple input signals and provide at least one latched output signal. ### Claim 15 (depends on 14) The integrated circuit of claim 14, wherein the one or more first latches comprise one or more first phase-two latches. ### Claim 16 (depends on 1) The integrated circuit of claim 1, wherein the read-write circuitry comprises a column multiplexer along with a write driver for write operations and a sense amplifier for read operations, wherein the column multiplexer comprises one or more second latches, and wherein each of the one or more second latches is configured to receive multiple input signals and provide at least one latched output signal. ### Claim 17 (depends on 14) The integrated circuit of claim 14, wherein the one or more second latches comprise one or more second phase-two latches.