# US 10,873,307 B2 · Power amplifier circuit

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- Number: US 10,873,307 B2
- Document ID: US10873307B2
- Status: Granted
- Kind: B2
- Application number: 16/223,297
- Filed: 2018-12-18
- Published: 2019-06-20
- Granted: 2020-12-22
- Earliest claimed: 2017-12-20
- Assignees: Murata Manufacturing Co., Ltd.
- Applicants: Murata Manufacturing Co., Ltd.
- Inventors: Masao Kondo; Satoshi Tanaka; Yasuhisa Yamamoto; Takayuki Tsutsui; Isao Obu
- Web page: https://patentgrep.com/patent/US10873307B2

## CPC

- H03G 3/3042: {in modulators, frequency-changers, transmitters or power amplifiers}
- H03F 1/0211: {with control of the supply voltage or current}
- H03F 1/301: {in MOSFET amplifiers (H03F1/303, H03F1/305, H03F1/308 take precedence)}
- H03F 1/302: {in bipolar transistor amplifiers (H03F1/303, H03F1/305, H03F1/307 take precedence)}
- H03F 3/195: in integrated circuits
- H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)}
- H03F 2200/211: the input of an amplifier can be attenuated by a continuously controlled transistor attenuator
- H03F 2200/222: A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
- H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F 2200/48: the output of the amplifier being coupled out by a capacitor
- H03F 2200/54: Two or more capacitor coupled amplifier stages in cascade
- H03F 2203/21103: An impedance adaptation circuit being added at the input of a power amplifier stage
- H03F 2203/21139: An impedance adaptation circuit being added at the output of a power amplifier stage
- H03G 2201/106: being attenuating element
- H03G 2201/40: Combined gain and bias control
- H03G: CONTROL OF AMPLIFICATION
- H03F: AMPLIFIERS

## Abstract

A power amplifier circuit includes a first transistor amplifying a first signal; a second transistor amplifying a second signal; a bias circuit supplying a bias current or voltage to a base or gate of the second transistor; and an attenuator attenuating the first or second signal in accordance with a control voltage supplied from the bias circuit. The attenuator includes a first diode to which the control voltage is supplied, a third transistor including a collector connected to a supply path of the first or second signal, an emitter connected to a ground, and a base to which the control voltage is supplied from the first diode, and a capacitor connected in parallel with the first diode. The control voltage decreases as a second signal power level increases. The third transistor allows part of the first or second signal to pass to the emitter in accordance with the control voltage.

## Claims

### Claim 1

A power amplifier circuit comprising:
a first transistor configured to amplify a first signal;
a second transistor configured to amplify a second signal, the second signal corresponding to an output signal of the first transistor;
a bias circuit configured to supply a bias current or a bias voltage to a base or a gate of the second transistor; and
an attenuation circuit configured to attenuate the first signal or the second signal based on a control voltage supplied from the bias circuit, wherein the attenuation circuit comprises:
a first diode element having an anode to which the control voltage is supplied,
a third transistor having a collector connected to a supply path of the first signal or a supply path of the second signal, an emitter connected to ground, and a base to which the control voltage is supplied from a cathode of the first diode element, and
a capacitor connected in parallel with the first diode element,
wherein the bias circuit is configured to decrease the supplied control voltage as a power level of the second signal increases, and
wherein the third transistor is configured to pass part of the first signal or the second signal from the collector of the third transistor to the emitter of the third transistor based on the control voltage.

### Claim 2

A power amplifier circuit comprising:
a first transistor configured to amplify a first signal;
a second transistor configured to amplify a second signal, the second signal corresponding to an output signal of the first transistor;
a bias circuit configured to supply a bias current or a bias voltage to a base or a gate of the second transistor; and
an attenuation circuit configured to attenuate the first signal or the second signal based on a control voltage supplied from the bias circuit,
wherein the attenuation circuit comprises:
a first diode element having an anode to which the control voltage is supplied, and
a third transistor having a base to which the control voltage is supplied from a cathode of the first diode element, a collector connected to the base of the third transistor and connected to a supply path of the first signal or a supply path of the second signal, and an emitter connected to ground,
wherein the bias circuit is configured to decrease the supplied control voltage as a power level of the second signal increases, and
wherein the third transistor is configured to pass part of the first signal or the second signal from the collector of the third transistor to the emitter of the third transistor based on the control voltage.

### Claim 3 (depends on 1)

The power amplifier circuit according to claim 1, wherein the bias circuit comprises a fourth transistor having an emitter from which the bias current or the bias voltage is output, and a base from which the control voltage is supplied.

### Claim 4 (depends on 2)

The power amplifier circuit according to claim 2, wherein the bias circuit comprises a fourth transistor having an emitter from which the bias current or the bias voltage is output, and a base from which the control voltage is supplied.

### Claim 5

A power amplifier circuit comprising:
a first transistor configured to amplify a first signal;
a second transistor configured to amplify a second signal, the second signal corresponding to an output signal of the first transistor;
a bias circuit configured to supply a bias current or a bias voltage to a base or a gate of the second transistor; and
an attenuation circuit configured to attenuate the first signal or the second signal based on a control voltage supplied from the bias circuit, wherein the attenuation circuit comprises:
a third transistor having a collector connected to a supply path of the first signal or a supply path of the second signal, a base to which the control voltage is supplied, and an emitter connected to ground,
wherein the bias circuit comprises:
a second diode element and a third diode element connected in series, a bias control voltage being supplied to an anode of the second diode element and a cathode of the third diode element being connected to ground, and
a fourth transistor having a base connected to the anode of the second diode element and an emitter from which the bias current or the bias voltage is output,
wherein the control voltage is supplied from an anode of the third diode element to the base of the third transistor, and
wherein the third transistor is configured to pass part of the first signal or the second signal from the collector of the third transistor to the emitter of the third transistor based on the control voltage.

### Claim 6 (depends on 1)

The power amplifier circuit according to claim 1, wherein the attenuation circuit further comprises:
a fourth diode element connected in series with the supply path to which the collector of the third transistor is connected, and
an inductor connected between a cathode of the fourth diode element and the ground.

### Claim 7 (depends on 2)

The power amplifier circuit according to claim 2, wherein the attenuation circuit further comprises:
a fourth diode element connected in series with the supply path to which the collector of the third transistor is connected, and
an inductor connected between a cathode of the fourth diode element and the ground.

### Claim 8 (depends on 5)

The power amplifier circuit according to claim 5, wherein the attenuation circuit further comprises:
a fourth diode element connected in series with the supply path to which the collector of the third transistor is connected, and
an inductor connected between a cathode of the fourth diode element and the ground.

### Claim 9 (depends on 1)

The power amplifier circuit according to claim 1, wherein the first transistor or the second transistor is a field-effect transistor (FET).

### Claim 10 (depends on 2)

The power amplifier circuit according to claim 2, wherein the first transistor or the second transistor is a field-effect transistor (FET).

### Claim 11 (depends on 5)

The power amplifier circuit according to claim 5, wherein the first transistor or the second transistor is a field-effect transistor (FET).