# US 10,873,301 B2 · Dual-input voltage memory digital pre-distortion circuit and related envelope tracking apparatus

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- Number: US 10,873,301 B2
- Document ID: US10873301B2
- Status: Granted
- Kind: B2
- Application number: 16/377,689
- Filed: 2019-04-08
- Published: 2020-10-08
- Granted: 2020-12-22
- Earliest claimed: 2019-04-08
- Assignees: Qorvo US, Inc.
- Applicants: Qorvo US, Inc.
- Inventors: Jean-Frederic Chiron
- Web page: https://patentgrep.com/patent/US10873301B2

## CPC

- H03F 1/3247: {using feedback acting on predistortion circuits (H03F1/3264 takes precedence)}
- H03F 1/0277: {Selecting one or more amplifiers from a plurality of amplifiers}
- H03F 1/3258: {based on polynomial terms}
- H03F 3/189: High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F 3/24: of transmitter output stages
- H03F 2200/102: A non-specified detector of a signal envelope being used in an amplifying circuit
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F 2201/3233: Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
- H03F: AMPLIFIERS

## Abstract

A dual-input voltage memory digital pre-distortion (mDPD) circuit and related ET apparatus are provided. In examples discussed herein, an ET apparatus includes an amplifier circuit(s) configured to amplify a radio frequency (RF) signal based on an ET voltage. A tracker circuit is configured to generate the ET voltage based on a number of target voltage amplitudes derived from a number of signal amplitudes of the RF signal. However, the tracker circuit can cause the ET voltage to deviate from the target voltage amplitudes due to various inherent impedance variations, particularly at a higher modulation bandwidth. In this regard, a dual-input voltage mDPD circuit is configured to digitally pre-distort the target voltage amplitudes based on the signal amplitudes such that the ET voltage can closely track the target voltage amplitudes. As such, it is possible to mitigate ET voltage deviation, thus helping to improve overall linearity performance of the ET apparatus.

## Claims

### Claim 1

A dual-input voltage memory digital pre-distortion (mDPD) circuit comprising:
a first port coupled to an input node of an envelope tracking (ET) engine circuit to receive a first digital signal having a plurality of signal amplitudes;
a second port coupled to an output node of the ET engine circuit to receive a second digital signal having a plurality of voltage amplitudes corresponding to the plurality of signal amplitudes; and
a control circuit configured to:
receive the first digital signal and the second digital signal from the first port and the second port, respectively; and
digitally pre-distort the plurality of voltage amplitudes based on the plurality of signal amplitudes to generate a digital target voltage signal having a plurality of target voltage amplitudes corresponding to the plurality of voltage amplitudes.

### Claim 2 (depends on 1)

The dual-input voltage mDPD circuit of claim 1 wherein the control circuit is further configured to digitally pre-distort the plurality of voltage amplitudes based on the plurality of signal amplitudes to correct one or more misalignments between the plurality of voltage amplitudes and the plurality of signal amplitudes in the plurality of target voltage amplitudes.

### Claim 3 (depends on 1)

The dual-input voltage mDPD circuit of claim 1 wherein the control circuit is further configured to execute a dual-input memory polynomial to digitally pre-distort the plurality of voltage amplitudes based on the plurality of signal amplitudes.

### Claim 4 (depends on 3)

The dual-input voltage mDPD circuit of claim 3 wherein the dual-input memory polynomial is a non-coupled memory polynomial (NCMP) expressed as:
y
⁡
[
n
]
=
[
K
0
0
,
0
+
∑
k
=
0
N
1
⁢
K
k
1
,
0
·
x
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
1
⁢
K
k
2
,
0
·
x
1
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
1
⁢
K
k
O
1
,
0
·
x
1
O
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
k
0
,
1
·
x
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
k
0
,
2
·
x
2
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
2
⁢
K
k
0
,
O
2
·
x
2
O
2
⁡
[
n
-
k
]
]
,
wherein:
y[n] represents a single output of a Volterra series;
x1 and x2 represent two inputs of the Volterra series;
K represents a kernel of the Volterra series;
K0 represents an offset term; and
O1 and O2 represent order terms of a respective path of a first input x1 and a respective path of a second input x2, respectively.

### Claim 5 (depends on 3)

The dual-input voltage mDPD circuit of claim 3 wherein the dual-input memory polynomial is a cross coupled memory polynomial (CCMP) expressed as:
y
⁡
[
n
]
=
[
K
0
0
,
0
+
∑
k
=
0
N
1
⁢
K
k
1
,
0
·
x
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
1
⁢
K
k
2
,
0
·
x
1
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
1
⁢
K
k
O
1
,
0
·
x
1
O
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
k
0
,
1
·
x
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
k
0
,
2
·
x
2
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
2
⁢
K
k
0
,
O
2
·
x
2
O
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
⁢
K
k
1
,
1
·
x
1
⁡
[
n
-
k
]
·
x
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
⁢
K
k
1
,
2
·
x
1
⁡
[
n
-
k
]
·
x
2
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
⁢
K
k
2
,
1
·
x
1
2
⁡
[
n
-
k
]
·
x
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
⁢
K
k
1
,
O
-
1
·
x
1
⁡
[
n
-
k
]
·
x
2
O
-
1
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
⁢
K
k
O
-
1
,
1
·
x
1
O
-
1
⁡
[
n
-
k
]
·
x
2
⁡
[
n
-
k
]
]
,
wherein:
y[n] represents a single output of a Volterra series;
x1 and x2 represent two inputs of the Volterra series;
K represents a kernel of the Volterra series;
K0 resents an offset term; and
O1 and O2 represent order terms of a respective path of a first input x1 and a respective path of a second input x2, respectively.

### Claim 6 (depends on 3)

The dual-input voltage mDPD circuit of claim 3 wherein the dual-input memory polynomial is a generalized cross coupled memory polynomial (GCCMP) expressed as:
y
⁡
[
n
]
=
[
K
0
,
0
0
,
0
+
∑
k
=
0
N
1
⁢
K
k
,
0
1
,
0
·
x
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
1
⁢
K
k
,
0
2
,
0
·
x
1
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
1
⁢
K
k
,
0
O
1
,
0
·
x
1
O
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
0
,
k
0
,
1
·
x
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
0
,
k
0
,
2
·
x
2
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
2
⁢
K
0
,
k
0
,
O
2
·
x
2
O
2
⁡
[
n
-
k
]
+
∑
[
k
1
,
k
2
]
∈
K
12
⁢
K
k
1
,
k
2
1
,
1
·
x
1
⁡
[
n
-
k
1
]
·
x
2
⁡
[
n
-
k
2
]
+
∑
[
k
1
,
k
2
]
∈
K
12
⁢
K
k
1
,
k
2
1
,
2
·
x
1
⁡
[
n
-
k
1
]
·
x
2
2
⁡
[
n
-
k
2
]
+
∑
[
k
1
,
k
2
]
∈
K
12
⁢
K
k
1
,
k
2
2
,
1
·
x
1
2
⁡
[
n
-
k
1
]
·
x
2
⁡
[
n
-
k
2
]
+
…
+
∑
[
k
1
,
k
2
]
∈
K
12
⁢
K
k
1
,
k
2
1
,
O
-
1
·
x
1
⁡
[
n
-
k
1
]
·
x
2
O
-
1
⁡
[
n
-
k
2
]
+
…
+
∑
[
k
1
,
k
2
]
∈
K
12
⁢
K
k
1
,
k
2
O
-
1
,
1
·
x
1
O
-
1
⁡
[
n
-
k
1
]
·
x
2
⁡
[
n
-
k
2
]
]
,
wherein:
y[n] represents a single output of a Volterra series;
x1 and x2 represent two inputs of the Volterra series;
K represents a kernel of the Volterra series;
K0 represents an offset term; and
O1 and O2 represent order terms of a respective path of a first input x1 and a respective path of a second input x2, respectively.

### Claim 7 (depends on 3)

The dual-input voltage mDPD circuit of claim 3 further comprising a training circuit configured to calibrate the dual-input memory polynomial based on a digital voltage feedback signal.

### Claim 8 (depends on 7)

The dual-input voltage mDPD circuit of claim 7 wherein the training circuit comprises:
an analog-to-digital converter (ADC) configured to receive and convert an analog voltage feedback signal into the digital voltage feedback signal;
timing adjustment circuitry configured to synchronize the plurality of signal amplitudes with the digital voltage feedback signal; and
a training controller configured to calibrate the dual-input memory polynomial based on the plurality of signal amplitudes, the plurality of target voltage amplitudes, and the digital voltage feedback signal.

### Claim 9 (depends on 1)

The dual-input voltage mDPD circuit of claim 1 further comprising a digital-to-analog converter (DAC) configured to convert the digital target voltage signal into an analog target voltage signal having a time-variant target voltage envelope corresponding to the plurality of target voltage amplitudes.

### Claim 10

An envelope tracking (ET) apparatus comprising:
an ET engine circuit comprising:
an input node configured to receive a first digital signal having a plurality of signal amplitudes; and
an output node configured to output a second digital signal having a plurality of voltage amplitudes corresponding to the plurality of signal amplitudes; and
a dual-input voltage memory digital pre-distortion (mDPD) circuit comprising:
a first port coupled to the input node of the ET engine circuit to receive the first digital signal having the plurality of signal amplitudes;
a second port coupled to the output node of the ET engine circuit to receive the second digital signal having the plurality of voltage amplitudes; and
a control circuit configured to:
receive the first digital signal and the second digital signal from the first port and the second port, respectively; and
digitally pre-distort the plurality of voltage amplitudes based on the plurality of signal amplitudes to generate a digital target voltage signal having a plurality of target voltage amplitudes corresponding to the plurality of voltage amplitudes.

### Claim 11 (depends on 10)

The ET apparatus of claim 10 wherein the dual-input voltage mDPD circuit further comprises a digital-to-analog converter (DAC) configured to convert the digital target voltage signal into an analog target voltage signal having a time-variant target voltage envelope corresponding to the plurality of target voltage amplitudes.

### Claim 12 (depends on 11)

The ET apparatus of claim 11 further comprising:
a tracker circuit configured to generate an ET voltage based on the analog target voltage signal, the ET voltage having a time-variant voltage envelope corresponding to the time-variant target voltage envelope; and
an amplifier circuit configured to amplify a radio frequency (RF) signal based on the ET voltage.

### Claim 13 (depends on 12)

The ET apparatus of claim 12 further comprising a signal processing circuit configured to:
receive a digital signal having a plurality of power amplitudes;
generate the first digital signal having the plurality of signal amplitudes corresponding to the plurality of power amplitudes;
provide the first digital signal to the ET engine circuit;
convert the digital signal into the RF signal having a time-variant power envelope corresponding to the plurality of power amplitudes; and
provide the RF signal to the amplifier circuit.

### Claim 14 (depends on 13)

The ET apparatus of claim 13 wherein the signal processing circuit comprises a signal mDPD circuit configured to:
receive the digital signal;
receive the second digital signal from the output node of the ET engine circuit; and
digitally pre-distort the plurality of power amplitudes in the digital signal based on the plurality of voltage amplitudes in the second digital signal.

### Claim 15 (depends on 10)

The ET apparatus of claim 10 wherein the control circuit is further configured to digitally pre-distort the plurality of voltage amplitudes based on the plurality of signal amplitudes to correct one or more misalignments between the plurality of voltage amplitudes and the plurality of signal amplitudes in the plurality of target voltage amplitudes.

### Claim 16 (depends on 10)

The ET apparatus of claim 10 wherein the control circuit is further configured to execute a dual-input memory polynomial to digitally pre-distort the plurality of voltage amplitudes based on the plurality of signal amplitudes.

### Claim 17 (depends on 16)

The ET apparatus of claim 16 wherein the dual-input memory polynomial is a non-coupled memory polynomial (NCMP) expressed as:
y
⁡
[
n
]
=
[
K
0
0
,
0
+
∑
k
=
0
N
1
⁢
K
k
1
,
0
·
x
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
1
⁢
K
k
2
,
0
·
x
1
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
1
⁢
K
k
O
1
,
0
·
x
1
O
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
k
0
,
1
·
x
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
k
0
,
2
·
x
2
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
2
⁢
K
k
0
,
O
2
·
x
2
O
2
⁡
[
n
-
k
]
]
,
wherein:
y[n] represents a single output of a Volterra series;
x1 and x2 represent two inputs of the Volterra series;
K represents a kernel of the Volterra series;
K0 represents an offset term; and
O1 and O2 represent order terms of a respective path of a first input x1 and a respective path of a second input x2, respectively.

### Claim 18 (depends on 16)

The ET apparatus of claim 16 wherein the dual-input memory polynomial is a cross coupled memory polynomial (CCMP) expressed as:
y
⁡
[
n
]
=
[
K
0
0
,
0
+
∑
k
=
0
N
1
⁢
K
k
1
,
0
·
x
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
1
⁢
K
k
2
,
0
·
x
1
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
1
⁢
K
k
O
1
,
0
·
x
1
O
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
k
0
,
1
·
x
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
k
0
,
2
·
x
2
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
2
⁢
K
k
0
,
O
2
·
x
2
O
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
⁢
K
k
1
,
1
·
x
1
⁡
[
n
-
k
]
·
x
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
⁢
K
k
1
,
2
·
x
1
⁡
[
n
-
k
]
·
x
2
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
⁢
K
k
2
,
1
·
x
1
2
⁡
[
n
-
k
]
·
x
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
⁢
K
k
1
,
O
-
1
·
x
1
⁡
[
n
-
k
]
·
x
2
O
-
1
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
⁢
K
k
O
-
1
,
1
·
x
1
O
-
1
⁡
[
n
-
k
]
·
x
2
⁡
[
n
-
k
]
]
,
wherein:
y[n] represents a single output of a Volterra series;
x1 and x2 represent two inputs of the Volterra series;
K rep resents a kernel of the Volterra series;
K0 represents an offset term; and
O1 and O2 represent order terms of a respective path of a first input x1 and a respective path of a second input x2, respectively.

### Claim 19 (depends on 16)

The ET apparatus of claim 16 wherein the dual-input memory polynomial is a generalized cross coupled memory polynomial (GCCMP) expressed as:
y
⁡
[
n
]
=
[
K
0
,
0
0
,
0
+
∑
k
=
0
N
1
⁢
K
k
,
0
1
,
0
·
x
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
1
⁢
K
k
,
0
2
,
0
·
x
1
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
1
⁢
K
k
,
0
O
1
,
0
·
x
1
O
1
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
0
,
k
0
,
1
·
x
2
⁡
[
n
-
k
]
+
∑
k
=
0
N
2
⁢
K
0
,
k
0
,
2
·
x
2
2
⁡
[
n
-
k
]
+
…
+
∑
k
=
0
N
2
⁢
K
0
,
k
0
,
O
2
·
x
2
O
2
⁡
[
n
-
k
]
+
∑
[
k
1
,
k
2
]
∈
K
12
⁢
K
k
1
,
k
2
1
,
1
·
x
1
⁡
[
n
-
k
1
]
·
x
2
⁡
[
n
-
k
2
]
+
∑
[
k
1
,
k
2
]
∈
K
12
⁢
K
k
1
,
k
2
1
,
2
·
x
1
⁡
[
n
-
k
1
]
·
x
2
2
⁡
[
n
-
k
2
]
+
∑
[
k
1
,
k
2
]
∈
K
12
⁢
K
k
1
,
k
2
2
,
1
·
x
1
2
⁡
[
n
-
k
1
]
·
x
2
⁡
[
n
-
k
2
]
+
…
+
∑
[
k
1
,
k
2
]
∈
K
12
⁢
K
k
1
,
k
2
1
,
O
-
1
·
x
1
⁡
[
n
-
k
1
]
·
x
2
O
-
1
⁡
[
n
-
k
2
]
+
…
+
∑
[
k
1
,
k
2
]
∈
K
12
⁢
K
k
1
,
k
2
O
-
1
,
1
·
x
1
O
-
1
⁡
[
n
-
k
1
]
·
x
2
⁡
[
n
-
k
2
]
]
,
wherein:
y[n] represents a single output of a Volterra series;
x1 and x2 represent two inputs of the Volterra series;
K represents a kernel of the Volterra series;
K0 represents an offset term; and
O1 and O2 represent order terms of a respective path of a first input x1 and a respective path of a second input x2, respectively.

### Claim 20 (depends on 16)

The ET apparatus of claim 16 wherein the dual-input voltage mDPD circuit further comprises a training circuit configured to calibrate the dual-input memory polynomial based on a digital voltage feedback signal.