# US 10,873,257 B2 · Low dropout regulator with smart offset

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- Number: US 10,873,257 B2
- Document ID: US10873257B2
- Status: Granted
- Kind: B2
- Application number: 16/563,160
- Filed: 2019-09-06
- Published: 2020-05-07
- Granted: 2020-12-22
- Earliest claimed: 2018-11-07
- Assignees: Regents of the University of Minnesota
- Applicants: Regents of the University of Minnesota
- Inventors: Ramesh Harjani; Saurabh Chaubey
- Web page: https://patentgrep.com/patent/US10873257B2

## CPC

- H02M 3/073: {Charge pumps of the Schenkel-type}
- G05F 1/565: sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence)
- G05F 1/575: characterised by the feedback circuit
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES

## Abstract

A low-dropout (LDO) regulator. The LDO regulator includes a pass transistor, a charge pump connected to the pass transistor, and an error amplifier connected through the charge pump to the pass transistor, wherein the error amplifier receives a voltage VO from the pass transistor and generates a voltage VE based on the voltage VO, wherein the charge pump receives the voltage VE from the error amplifier, generates a voltage VE* that is lower than VE by an offset and supplies the voltage VE* as a gate voltage to the pass transistor.

## Claims

### Claim 1

A low-dropout (LDO) regulator, comprising:
a pass transistor;
a charge pump connected to the pass transistor; and
an error amplifier connected through the charge pump to the pass transistor, wherein the error amplifier receives a voltage Vo from the pass transistor and generates a voltage VE based on the voltage VO and a reference voltage; and
wherein the charge pump receives the voltage VE from the error amplifier, generates a voltage VE* that is lower than VE by an offset and supplies the voltage VE* as a gate voltage to the pass transistor,
wherein the charge pump includes four capacitors A-D operating during two non-overlapping phases, Φ1 and Φ2, wherein during phase Φ1 capacitor A gets charged to VE, capacitor B gets charged to VDD/2 and capacitors C and D get charged to approximately 0.5V, and wherein during phase Φ2 all the capacitors are connected in series with the capacitors C and D having opposite polarity.

### Claim 2 (depends on 1)

The LDO regulator of claim 1, wherein the offset is a fixed offset.

### Claim 3 (depends on 1)

The LDO regulator of claim 1, wherein the error amplifier is a self-biased operational-transconductance-amplifier (OTA) design.

### Claim 4 (depends on 3)

The LDO regulator of claim 3, wherein the error amplifier is a self-biased folded cascode OTA.

### Claim 5 (depends on 4)

The LDO regulator of claim 4, wherein the error amplifier is a bulk-driven Miller OTA.

### Claim 6 (depends on 1)

The LDO regulator of claim 1, wherein the error amplifier is an inverter-based amplifier.

### Claim 7 (depends on 1)

The LDO regulator of claim 1, wherein the charge pump includes a fast-switched capacitor charge pump network.

### Claim 8 (depends on 1)

The LDO regulator of claim 1, wherein the charge pump operates at a frequency such that charge pump ripple is attenuated by closed loop control of the regulator.

### Claim 9

A low-dropout (LDO) regulator, comprising:
a pass transistor;
a charge pump connected to the pass transistor; and
an error amplifier connected through the charge pump to the pass transistor, wherein the error amplifier receives a voltage VO from the pass transistor and generates a voltage VE based on the voltage VO and a reference voltage; and
wherein the charge pump receives the voltage VE from the error amplifier, generates a voltage VE* that is lower than VE by an offset and supplies the voltage VE* as a gate voltage to the pass transistor,
wherein the charge pump includes a fast-switched capacitor charge pump network, and
wherein the fast-switched capacitor charge pump network operates on non-overlapping phases Φ1 and Φ2 generated by a ring oscillator coupled to a non-overlapping clock generator.

### Claim 10 (depends on 9)

The LDO regulator of claim 9, wherein the ring oscillator is a 32-stage ring oscillator.

### Claim 11

A negative voltage offset low-dropout (NVO-LDO) regulator, comprising:
a pass transistor; and
a negative voltage offset circuit connected to the pass transistor, wherein the negative voltage offset circuit receives an error voltage VE, forms an offset error voltage VE*, and applies the offset error voltage VE* to a gate of the pass transistor, wherein forming includes operating four switched capacitors A-D during two non-overlapping phases, Φ1 and Φ2 such that:
during phase Φ1, capacitor A gets charged to the error voltage VE, capacitor B gets charged to VDD/2 and capacitors C and D get charged to 0.5V, and
during phase Φ2, all the capacitors are connected in series with the capacitors C and D having opposite polarity.

### Claim 12

A negative voltage offset low-dropout (NVO-LDO) regulator, comprising:
a pass transistor; and
a charge pump connected to the pass transistor, wherein the charge pump includes four switched capacitors A-D and wherein the charge pump:
receives an error voltage VE;
forms an offset error voltage VE*, wherein forming includes operating the four switched capacitors A-D in the charge pump during two non-overlapping phases, Φ1 and Φ2, such that:
during phase Φ1, capacitor A gets charged to the error voltage VE, capacitor B gets charged to VDD/2 and capacitors C and D get charged to ≈0.5V, and
during phase Φ2, all the capacitors are connected in series with the capacitors C and D having opposite polarity; and
applies the offset error voltage VE* to a gate of the pass transistor.

### Claim 13 (depends on 12)

The regulator of claim 12, wherein the charge pump operates at a frequency such that charge pump ripple is attenuated by closed loop control of the regulator.

### Claim 14

In an LDO regulator having a supply voltage VDD, a method, comprising:
receiving an error voltage VE; and
generating an offset error voltage VE* from the error voltage VE, wherein generating includes operating a charge pump having four switched capacitors A-D using a clock having two non-overlapping phases, Φ1 and Φ2, such that:
during phase Φ1, capacitor A gets charged to the error voltage VE, capacitor B gets charged to VDD/2 and capacitors C and D get charged to 0.5V, and
during phase Φ2, all the capacitors are connected in series with the capacitors C and D having opposite polarity.

### Claim 15 (depends on 14)

The method of claim 14, wherein the LDO has a closed loop control and wherein the clock has a frequency selected such that charge pump ripple is attenuated by the closed loop control.

### Claim 16

An LDO regulator, comprising:
a pass transistor connected to an LDO supply voltage VDD; and
an offset module connected to the pass transistor, wherein the offset module receives an error voltage VE, and provides a voltage VE* to a gate of the pass transistor, wherein VE*=VE-VOS, where VOS=A-A×VDD, where A is a number greater than zero and less than one,
wherein the offset module includes a charge pump having four capacitors A-D operating during two non-overlapping phases, Φ1 and Φ2,
wherein during phase Φ1 capacitor A is charged to approximately VE capacitor B is charged to approximately A×VDD and capacitors C and D are charged to approximately A Volts, and
wherein during phase Φ2 all the capacitors are connected in series with the capacitors C and D having opposite polarity.

### Claim 17 (depends on 16)

The LDO regulator of claim 16, wherein A=0.5.

### Claim 18 (depends on 16)

The LDO regulator of claim 16, wherein A is a function of lithography.