# US 10,873,128 B2 · TFT substrate, scanned antenna having TFT substrate, and method for manufacturing TFT substrate

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- Number: US 10,873,128 B2
- Document ID: US10873128B2
- Status: Granted
- Kind: B2
- Application number: 16/191,953
- Filed: 2018-11-15
- Published: 2019-05-16
- Granted: 2020-12-22
- Earliest claimed: 2017-11-16
- Assignees: Sharp Kabushiki Kaisha
- Applicants: Sharp Kabushiki Kaisha
- Inventors: Kenichi Kitoh; Fumitoshi Yasuo; Shinya Kadono; Junichi Inukai; Juxian Li
- Web page: https://patentgrep.com/patent/US10873128B2

## CPC

- H01Q 1/38: formed by a conductive layer on an insulating support {(patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142)}
- G02F 1/1343: Electrodes {(reflective electrodes G02F1/133553)}
- H01Q 1/364: {using a particular conducting material, e.g. superconductor}
- H01Q 3/44: varying the electric or magnetic characteristics of reflecting, refracting, or diffracting devices associated with the radiating element
- H01Q 21/0087: {Apparatus or processes specially adapted for manufacturing antenna arrays (manufacturing waveguides H01P11/00)}
- H01Q 21/064: {using horn or slot aerials (slotted waveguides arrays H01Q21/005)}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 86/40: characterised by multiple TFTs
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72)
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A TFT substrate includes a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate. Each of the plurality of antenna unit regions has a TFT and a patch electrode electrically connected to the drain electrode of the TFT. The patch electrode includes a first electrode layer formed of the same conductive film as the gate electrode of the TFT and a second electrode layer formed of the same conductive film as the source electrode of the TFT.

## Claims

### Claim 1

A TFT substrate comprising:
a dielectric substrate;
a plurality of antenna unit regions arranged on the dielectric substrate and each having a TFT and a patch electrode electrically connected to a drain electrode of the TFT,
wherein the patch electrode includes a first electrode layer formed of a conductive film identical to a conductive film of a gate electrode of the TFT and a second electrode layer formed of a conductive film identical to a conductive film of a source electrode of the TFT,
the TFT substrate further comprising:
a gate metal layer supported on the dielectric substrate and including the gate electrode and the first electrode layer;
a semiconductor layer of the TFT supported on the dielectric substrate;
a gate insulating layer formed between the semiconductor layer and the gate metal layer;
a source metal layer supported on the dielectric substrate and including the source electrode, the drain electrode, and the second electrode layer,
an interlayer insulating layer formed on the gate metal layer and the source metal layer; and
an upper conductive layer formed on the interlayer insulating layer,
wherein the interlayer insulating layer has an opening portion reaching the first electrode layer or the second electrode layer,
the patch electrode further includes a third electrode layer connected to the first electrode layer or the second electrode layer in the opening portion,
the third electrode layer is included in the upper conductive layer, and
the third electrode layer is formed to cover a portion of the first electrode layer or the second electrode layer which is exposed in the opening portion.

### Claim 2 (depends on 1)

The TFT substrate according to claim 1,
wherein the first electrode layer includes a Cu layer or an Al layer.

### Claim 3 (depends on 1)

The TFT substrate according to claim 1,
wherein the second electrode layer includes a Cu layer or an Al layer.

### Claim 4 (depends on 1)

The TFT substrate according to claim 1,
wherein the first electrode layer has a thickness of 100 nm or more and 1000 nm or less.

### Claim 5 (depends on 1)

The TFT substrate according to claim 1,
wherein the second electrode layer has a thickness of 100 nm or more and 1000 nm or less.

### Claim 6 (depends on 1)

The TFT substrate according to claim 1,
wherein the second electrode layer is formed on the first electrode layer.

### Claim 7 (depends on 1)

A scanning antenna comprising:
the TFT substrate according to claim 1;
a slot substrate arranged to face the TFT substrate;
a liquid crystal layer provided between the TFT substrate and the slot substrate; and
a reflective conductive plate arranged to face a surface of the slot substrate on an opposite side to the liquid crystal layer via a dielectric layer,
wherein the slot substrate has another dielectric substrate, and a slot electrode formed on a surface of the other dielectric substrate on a side of the liquid crystal layer,
the slot electrode has a plurality of slots, and each of the plurality of slots is arranged to correspond to the patch electrode in each of the plurality of antenna unit regions of the TFT substrate.

### Claim 8 (depends on 1)

A method of manufacturing the TFT substrate according to claim 1, the method comprising:
(A) forming a gate conductive film on the dielectric substrate;
(B) forming the gate electrode and the first electrode layer by patterning the gate conductive film;
(C) depositing a gate insulating film which covers the gate electrode and the first electrode layer;
(D) forming a first opening portion reaching the first electrode layer in the gate insulating film;
(E) forming a source conductive film on the gate insulating film and in the first opening portion; and
(F) forming the source electrode and the second electrode layer by patterning the source conductive film.

### Claim 9 (depends on 8)

The method of manufacturing a TFT substrate according to claim 8, further comprising:
(G) depositing an interlayer insulating film which covers the source electrode and the second electrode layer;
(H) etching the interlayer insulating film;
(I) forming an upper conductive film on the interlayer insulating film after (H); and
(J) patterning the upper conductive film.

### Claim 10 (depends on 9)

The method of manufacturing a TFT substrate according to claim 9,
wherein (H) includes forming the opening portion reaching the second electrode layer, and (J) includes forming the third electrode layer connected to the second electrode layer in the opening portion.

### Claim 11

A method of manufacturing a TFT substrate,
the TFT substrate comprising:
a dielectric substrate;
a plurality of antenna unit regions arranged on the dielectric substrate and each having a TFT and a patch electrode electrically connected to a drain electrode of the TFT,
wherein the patch electrode includes a first electrode layer formed of a conductive film identical to a conductive film of a gate electrode of the TFT and a second electrode layer formed of a conductive film identical to a conductive film of a source electrode of the TFT, and
the method comprising:
(A) forming a gate conductive film on the dielectric substrate;
(B) forming the gate electrode and the first electrode layer by patterning the gate conductive film;
(C) depositing a gate insulating film which covers the gate electrode and the first electrode layer;
(D) forming a first opening portion reaching the first electrode layer in the gate insulating film;
(E) forming a source conductive film on the gate insulating film and in the first opening portion; and
(F) forming the source electrode and the second electrode layer by patterning the source conductive film.

### Claim 12 (depends on 11)

The method of manufacturing a TFT substrate according to claim 11, further comprising:
(G) depositing an interlayer insulating film which covers the source electrode and the second electrode layer;
(H) etching the interlayer insulating film;
(I) forming an upper conductive film on the interlayer insulating film after (H); and
(J) patterning the upper conductive film.

### Claim 13 (depends on 12)

The method of manufacturing a TFT substrate according to claim 12,
wherein (H) includes forming a second opening portion reaching the second electrode layer, and (J) includes forming a third electrode layer connected to the second electrode layer in the second opening portion.