# US 10,872,985 B2 · Zero cost NVM cell using high voltage devices in analog process > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,985 B2 - Document ID: US10872985B2 - Status: Granted - Kind: B2 - Application number: 14/996,653 - Filed: 2016-01-15 - Published: 2016-06-16 - Granted: 2020-12-22 - Earliest claimed: 2011-05-10 - Assignees: Jonker LLC - Applicants: David Liu - Inventors: David Liu - Web page: https://patentgrep.com/patent/US10872985B2 ## CPC - H10D 30/685: {from the channel} - H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates - H10B 41/10: characterised by the top-view layout - H10B 41/30: characterised by the memory core region - H10B 41/47: with a floating-gate layer also being used as part of the peripheral transistor - H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell - H10D 30/0411: {of FETs having floating gates} - H10D 30/65: Lateral DMOS [LDMOS] FETs - H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling} - H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc. ## Claims ### Claim 1 A method of forming a programmable non-volatile memory device in a high voltage circuit portion of a substrate comprising: forming a floating gate on a surface of the high voltage circuit portion of a substrate; forming a source region in the high voltage circuit portion of a substrate; forming a drain region in the high voltage circuit portion of a substrate; forming a drift region with a first portion overlapping part of said drain region and a second portion overlapping part of said floating gate in a direction perpendicular to the substrate, the drift region comprising a notch extending into the drift region in a direction away from the source region; wherein the drain region has an extension protruding from the drain region into the notch and overlapping a first edge of the floating gate in a direction perpendicular to the substrate, an electron infection region is formed by said drain extension and said first edge of said floating gate, and the notched drift region overlaps a sufficient portion of the floating gate such that a programming voltage for the device can be imparted to said floating gate through areal capacitive coupling. ### Claim 2 (depends on 1) The method of claim 1, wherein completing said programmable nonvolatile memory device only requires manufacturing steps also used to make high voltage devices in the high voltage circuit portion of the substrate. ### Claim 3 A method of forming a programmable non-volatile memory device in a high voltage circuit portion of a substrate comprising; forming a floating gate on a surface of the high voltage circuit portion of a substrate; forming a source for the device in the high voltage circuit portion of a substrate; forming a drain for the device in the high voltage circuit portion of a substrate; forming a drift region also having said first impurity type with a first portion overlapping part of said drain and a second portion overlapping part of said floating gate in a direction perpendicular to the substrate, the drift region comprising a notch extending into the drift region in a direction away from the source region; wherein the drain region has an extension protruding from the drain region into the notch and overlapping a first edge of the floating gate in a direction perpendicular to the substrate, an injection region having a first impurity type formed by said drain extension abutting said first edge of said floating gate is adapted to permit programming of the device through channel hot electron injection to said floating gate, and the drift region overlaps a sufficient portion of the floating gate such that a programming voltage for the device can be imparted to said floating gate through areal capacitive coupling. ### Claim 4 (depends on 3) The method of claim 3 wherein said drift region includes a notched shape. ### Claim 5 (depends on 3) The method of claim 3 wherein a coupling ratio is dependent on a size of said second portion of said drift region overlapping said floating gate. ### Claim 6 (depends on 3) The method of claim 3 wherein a polysilicon layer used for said floating gate is used for forming gates for high voltage transistor devices. ### Claim 7 (depends on 3) The method of claim 3 wherein the device shares structures and regions used by lateral high voltage devices in said high voltage circuit portion of the substrate. ### Claim 8 (depends on 3) The method of claim 3 further including a step: performing an implant for said drift region using a mask to impart a first shape for the device drift region that is different from a second shape imparted to a high voltage device in said high voltage circuit portion of the substrate. ### Claim 9 (depends on 8) The method of claim 8 further including a step: performing an implant for said source and drain a mask to impart a first shape for the device source and drain that is different from a second shape imparted to source and drain of a high voltage device in said high voltage circuit portion of the substrate. ### Claim 10 (depends on 3) The method of claim 3 wherein the device is formed with a thicker oxide than that used by logic devices in a portion separate from said high voltage circuit portion. ### Claim 11 (depends on 9) The method of claim 9 wherein the device is configured as a one-time programmable memory. ### Claim 12 (depends on 3) The method of claim 3 wherein the device is formed with a gate oxide that is the same as that used by high voltage devices in said high voltage circuit portion. ### Claim 13 (depends on 12) The method of claim 12 wherein the device is configured as a multiple time programmable memory. ### Claim 14 A method of forming a programmable non-volatile memory device in a high voltage circuit portion of a substrate comprising; forming a floating gate on a surface of the high voltage circuit portion of a substrate; forming a source region in the high voltage circuit portion of a substrate; forming an N-type drain region in the high voltage circuit portion of a substrate; forming an N-type drift region with a notch extending into the drift region in a direction away from the source region, and such that a first portion of said N-type drift region overlaps part of said N-type drain region and a second portion of said N-type drift region overlaps part of said floating gate in a direction perpendicular to the substrate; wherein the drain region has an extension protruding from the drain region into the notch and overlapping a first edge of the floating gate in a direction perpendicular to the substrate, an injection region having a first impurity type formed by said drain extension abutting said first edge of said floating gate is adapted to permit programming of the device through channel hot electron injection to said floating gate, and said second portion of said N-type drift region overlaps a sufficient portion of the floating gate such that a programming voltage for the device can be imparted to said floating gate through areal capacitive coupling to said N-type drain region; further wherein the programmable non-volatile memory device as formed does not include or require a control gate to operate. ### Claim 15 (depends on 14) The method of claim 14 wherein the programmable non-volatile memory device is fabricated using only components also associated with a lateral extended drain NMOS device and/or a lateral double-diffused NMOS device. ### Claim 16 (depends on 1) The method of claim 1 wherein the programmable non-volatile memory device is a result of alterations to a high voltage device drift region mask and a high voltage source/drain mask. ### Claim 17 (depends on 1) The method of claim 1 wherein the drift region is C-shaped and said drain extension is formed from the notch. ### Claim 18 (depends on 1) The method of claim 1 wherein the programmable non-volatile memory device is fabricated using only components also associated with a lateral extended drain NMOS device and/or a lateral double-diffused NMOS device. ### Claim 19 (depends on 3) The method of claim 3 wherein said first impurity type is N-type. ### Claim 20 (depends on 3) The method of claim 3 wherein the programmable non-volatile memory device is a result of alterations to a high voltage device drift region mask and a high voltage source/drain mask.