# US 10,872,984 B2 · Thin film transistor having channel regions, array substrate, manufacturing method thereof and display device comprising the same

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- Number: US 10,872,984 B2
- Document ID: US10872984B2
- Status: Granted
- Kind: B2
- Application number: 16/135,511
- Filed: 2018-09-19
- Published: 2019-05-02
- Granted: 2020-12-22
- Earliest claimed: 2017-10-27
- Assignees: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd.
- Inventors: Jinjin Xue; Dawei Shi; Haifeng Xu; Lu Yang; Wentao Wang; Lei Yan; Lei Yao; Fang Yan; Xiaowen Si
- Web page: https://patentgrep.com/patent/US10872984B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- G02F 1/134309: {characterised by their geometrical arrangement}
- G02F 1/1362: Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- H10D 30/6723: {having light shields}
- H10D 30/6733: {Multi-gate TFTs}
- H10D 30/674: {characterised by the active materials}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 2201/121: common or background
- G02F 2201/123: pixel
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

A thin-film transistor (TFT), an array substrate, a manufacturing method thereof and a display device are provided. The TFT includes an active layer, a gate electrode, a first source/drain electrode and a second source/drain electrode. The active layer includes a first channel region and a second channel region, a first source/drain area between the first channel region and the second channel region, and a second source/drain area opposite to the first source/drain area through the first channel region or the second channel region. The gate electrode includes a first gate electrode and a second gate electrode which are respectively overlapped with the first channel region and the second channel region. The first source/drain electrode and the second source/drain electrode are respectively electrically connected with the first source/drain area and the second source/drain area of the active layer.

## Claims

### Claim 1

A thin-film transistor (TFT), comprising:
an active layer including a first channel region and a second channel region, a first source/drain area between the first channel region and the second channel region, and a second source/drain area opposite to the first source/drain area through the first channel region or the second channel region;
a gate electrode including a first gate electrode and a second gate electrode, wherein the first gate electrode and the second gate electrode are respectively overlapped with the first channel region and the second channel region, and the first gate electrode and the second gate electrode are electrically connected; and
a first source/drain electrode and a second source/drain electrode being respectively electrically connected with the first source/drain area and the second source/drain area of the active layer.

### Claim 2 (depends on 1)

The TFT according to claim 1, wherein the second source/drain area includes a first sub-source/drain area and a second sub-source/drain area; and the second source/drain electrode is electrically connected with both the first sub-source/drain area and the second sub-source/drain area.

### Claim 3 (depends on 1)

The TFT according to claim 1, further comprising an interlayer insulating layer, wherein the interlayer insulating layer is provided between the active layer and the first source/drain electrode and the second source/drain electrode and provided with a plurality of through holes for the first source/drain electrode and the second source/drain electrode to be respectively electrically connected with the active layer.

### Claim 4 (depends on 1)

The TFT according to claim 1, wherein
the active layer is a closed pattern; and the second source/drain area is provided between the first channel region and the second channel region.

### Claim 5 (depends on 4)

The TFT according to claim 4, wherein the closed pattern is a circle or a polygon.

### Claim 6 (depends on 5)

The TFT according to claim 5, wherein the polygon is a rectangle.

### Claim 7 (depends on 1)

The TFT according to claim 1, wherein the active layer includes material of polycrystalline silicon (poly-Si).

### Claim 8 (depends on 1)

The TFT according to claim 1, wherein the first gate electrode and the second gate electrode are a same structure.

### Claim 9 (depends on 1)

The TFT according to claim 1, wherein the TFT adopts top-gate or bottom-gate type.

### Claim 10 (depends on 1)

An array substrate, comprising the thin film transistor (TFT) according to claim 1.

### Claim 11 (depends on 10)

The array substrate according to claim 10, further comprising:
a pixel electrode electrically connected with one of the first source/drain electrode and the second source/drain electrode; and
a common electrode which forms two electrodes of a first capacitor together with the pixel electrode.

### Claim 12 (depends on 11)

The array substrate according to claim 11, wherein the common electrode and the pixel electrode are in different layers.

### Claim 13 (depends on 11)

The array substrate according to claim 11, further comprising:
a metal layer provided in a same layer as the first source/drain electrode and the second source/drain electrode or the gate electrode, the metal layer being at least partially overlapped with the active layer and configured to form two electrodes of a second capacitor together with the active layer.

### Claim 14 (depends on 13)

The array substrate according to claim 13, wherein the metal layer is electrically connected with the common electrode.

### Claim 15 (depends on 10)

The array substrate according to claim 10, further comprising:
a light blocking layer at least overlapped with at least one of the first channel region and the second channel region of the active layer.

### Claim 16 (depends on 10)

A display device, comprising the array substrate according to claim 10.

### Claim 17

A method for manufacturing an array substrate, comprising:
forming an active layer, in which the active layer includes a first channel region and a second channel region, a first source/drain area between the first channel region and the second channel region, and a second source/drain area opposite to the first source/drain area through the first channel region or the second channel region;
forming a gate electrode, wherein the gate electrode includes a first gate electrode and the second gate electrode respectively overlapped with the first channel region and the second channel region, and the first gate electrode and the second gate electrode are electrically connected; and
forming a first source/drain electrode and a second source/drain electrode, in which the first source/drain electrode and the second source/drain electrode are respectively connected with the first source/drain area and the second source/drain area of the active layer.

### Claim 18 (depends on 17)

The method for manufacturing the array substrate according to claim 17, wherein
the active layer is a closed pattern; and the second source/drain area is formed between the first channel region and the second channel region.

### Claim 19 (depends on 17)

The method for manufacturing the array substrate according to claim 17, further comprising:
forming a pixel electrode electrically connected with one of the first source/drain electrode and the second source/drain electrode; and
forming a common electrode which form two electrodes of a first capacitor together with the pixel electrode.

### Claim 20 (depends on 19)

The method for manufacturing the array substrate according to claim 19, further comprising:
forming a metal layer, in which
the metal layer is simultaneously formed with the first source/drain electrode and the second source/drain electrode or the gate electrode, the metal layer is at least partially overlapped with the active layer and forms two electrodes of a second capacitor together with the active layer.