# US 10,872,983 B2 · Semiconductor devices and manufacturing methods thereof

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- Number: US 10,872,983 B2
- Document ID: US10872983B2
- Status: Granted
- Kind: B2
- Application number: 15/900,175
- Filed: 2018-02-20
- Published: 2019-02-28
- Granted: 2020-12-22
- Earliest claimed: 2017-08-29
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jung Gil Yang; Woo Seok Park; Dong Chan Suh; Seung Min Song; Geum Jong Bae; Dong Il Bae
- Web page: https://patentgrep.com/patent/US10872983B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/503: {having non-rectangular cross-sections}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a plurality of channel layers stacked on the substrate, the plurality of channel layers comprising a first channel layer and a second channel layer;
a gate electrode surrounding the plurality of channel layers; and
embedded source/drain layers on opposing sides of the gate electrode, the embedded source/drain layers each having a first region and a second region that is on the first region, the second region comprising a plurality of layers having different compositions,
wherein lateral surfaces of the second channel layer adjacent to the embedded source/drain layers are inclined with respect to an upper surface of the substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
interfacial layers comprising first portions that are between the embedded source/drain layers and the plurality of channel layers and comprising a second portion that is between the embedded source/drain layers and the substrate,
wherein a first composition of the first region is different from a second composition of at least one of the interfacial layers, and
wherein each of the first portions and the second portion are spaced apart from each other in a direction perpendicular to the upper surface of the substrate.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first region and the plurality of channel layers both comprise a first semiconductor material, and
wherein the interfacial layers and the second region both comprise a second semiconductor material.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first region further comprises p-type impurities.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second region comprises a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer sequentially stacked on the first region.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer comprise a silicon germanium compound,
wherein a third germanium content of the third epitaxial layer is higher than a second germanium content of the second epitaxial layer, and
wherein the second germanium content of the second epitaxial layer is higher than a first germanium content of the first epitaxial layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a length of at least a region of the second channel layer is greater than a length of the first channel layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the lateral surfaces of the second channel layer adjacent to the embedded source/drain layers are flat surfaces that are inclined with respect to the upper surface of the substrate.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the lateral surfaces of the second channel layer adjacent to the embedded source/drain layers are curved surfaces that are inclined with respect to the upper surface of the substrate.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein a length of an upper portion of the second channel layer is greater than a length of a lower portion of the second channel layer.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of channel layers further comprise a third channel layer,
wherein the third channel layer has a length decreasing toward the substrate, and
wherein the first channel layer has a length increasing toward the substrate.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein respective ones of the plurality of channel layers have a thickness in a first direction perpendicular to the substrate that is less than a width in a second direction crossing the first direction.

### Claim 13

A semiconductor device, comprising:
a substrate;
a plurality of channel layers stacked on the substrate, the plurality of channel layers extending in a first direction;
a gate electrode surrounding the plurality of channel layers, the gate electrode extending in a second direction, intersecting the first direction; and
embedded source/drain layers on opposing sides of the gate electrode,
wherein at least one first channel layer of the plurality of channel layers has a region having a first length extending farther in the first direction than a second length of a second channel layer of the plurality of channel layers that is adjacent to the first channel layer,
wherein the embedded source/drain layers each have a first region and a second region that is on the first region, and
wherein the second region comprises a plurality of layers having different compositions.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein a top channel layer of the plurality of channel layers that is farthest from the substrate has an inclined lateral surface.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein a top channel layer of the plurality of channel layers that is farthest from the substrate has a length extending in the first direction that decreases toward the substrate.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, further comprising:
interfacial layers between the embedded source/drain layers and the plurality of channel layers and between the embedded source/drain layers and the substrate.