# US 10,872,978 B2 · Metal gate structure and methods of fabricating thereof

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- Number: US 10,872,978 B2
- Document ID: US10872978B2
- Status: Granted
- Kind: B2
- Application number: 16/673,512
- Filed: 2019-11-04
- Published: 2020-02-27
- Granted: 2020-12-22
- Earliest claimed: 2017-11-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: I-Wei Yang; Chih-Chang Hung; Shu-Yuan Ku; Ryan Chia-Jen Chen; Ming-Ching Chang
- Web page: https://patentgrep.com/patent/US10872978B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0153: {using gate cut processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 50/267: {using plasmas}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/48: Insulating materials thereof
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/6902: {composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/6922: {the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC}
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a first fin and a second fin each extending from a substrate, wherein the first fin and the second fin each have a length extending in a first direction;
a first metal gate over the first fin and a second metal gate over the second fin, wherein the first metal gate and the second metal gate each have a length greater than a width, wherein the length extends in a second direction perpendicular the first direction;
at least one dielectric layer adjacent the first metal gate and the second metal gate; and
a cut region extending between the first and second metal gates, wherein the cut region has a first portion having a first width and a second portion having a second width, the second width greater than the first width and wherein the second portion interposes the first and second metal gates and the first portion is defined within the at least one dielectric layer, wherein the first width and the second width are measured from a top view.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a sidewall of the cut region that extends from the first portion to the second portion is disposed at an angle Θ relative to a plane perpendicularly oriented to a length of the first fin and perpendicularly oriented to a top surface of the substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first width is defined from a first point on an interlayer dielectric (ILD) layer of the at least one dielectric layer to a second point on the ILD layer of the at least one dielectric layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the cut region is filled with dielectric material.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the cut region extends into a shallow trench isolation feature between the first fin and the second fin.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the cut region has a third width at a top surface of the shallow trench isolation feature and the second width between the first metal gate and the second metal gate above the third width, wherein the third width and second width are measured on a plane parallel to a top surface of the substrate.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first metal gate has a first substantially linear sidewall and the second metal gate has a second substantially linear sidewall, wherein the at least one dielectric layer extends between the first and second substantially linear sidewalls.

### Claim 8

A semiconductor device, comprising:
a first fin and a second fin extending from a semiconductor substrate, wherein a shallow trench isolation (STI) extends between the first and second fins;
a first gate structure extending over the first fin and a second gate structure extending over the second fin, the first and second gate structures being collinear;
a first dielectric layer between the first gate structure and the second gate structure;
a dielectric region interposing the first gate structure and the second gate structure, the dielectric region extending at least to a top surface of the STI, wherein the dielectric region has:
a first portion of the dielectric region having a first width, the first portion defined by a first sidewall of the first gate structure and a second sidewall of the second gate structure;
a second portion of the dielectric region having a second width, the second portion of the dielectric region has edges defined by the first dielectric layer, and wherein the first width is greater than the second width; and
a third portion of the dielectric region being disposed between the first portion and the second portion in a top view.

### Claim 9 (depends on 8)

The device of claim 8, wherein the third portion of the opening includes a sidewall disposed an angle Θ, wherein the angle Θ is less than 45 degrees from a plane parallel a sidewall of the first gate structure.

### Claim 10 (depends on 8)

The device of claim 8, wherein the first dielectric layer is an interlayer dielectric (ILD) layer.

### Claim 11 (depends on 10)

The device of claim 10, wherein a spacer layer abuts the first gate structure and the ILD layer.

### Claim 12 (depends on 8)

The device of claim 8, wherein the first gate structure and the second gate structure include a high-k dielectric layer.

### Claim 13

A method of semiconductor device fabrication including:
cutting a metal gate structure into a first metal gate segment and a collinear second metal gate segment wherein the cutting includes:
performing a first process to deposit a silicon layer;
performing an etch of a metal layer of the metal gate structure, wherein the etch includes at least one of a high bias or high duty cycle;
performing a polymer deposition step; and
repeating the first process, the etch, and the polymer deposition step.

### Claim 14 (depends on 13)

The method of claim 13, wherein the performing the etch includes the high bias having a power greater than about 1500 Watts (W) and a bias voltage over about 60 Volts (V).

### Claim 15 (depends on 13)

The method of claim 13, wherein the performing the etch includes the high duty cycle having a duty cycle of greater than about 25%.

### Claim 16 (depends on 13)

The method of claim 13, wherein the cutting forms an opening in the metal gate structure and an adjacent dielectric layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein a width of the opening in the metal gate structure is greater than a width of the opening in the adjacent dielectric layer, the width being measured on a plane parallel a top surface of a semiconductor substrate comprising the metal gate structure.

### Claim 18 (depends on 13)

The method of claim 13, wherein the cutting forms an opening in the metal gate structure and an underlying shallow trench isolation (STI) feature.

### Claim 19 (depends on 18)

The method of claim 18, wherein a first width of the opening in the metal gate structure is less than a second width of the opening in the STI feature, each of the first width and the second width being measured on a plane parallel a length of the metal gate structure, the first width defined on a plane above the second width.

### Claim 20 (depends on 13)

The method of claim 13, wherein the repeating is performed seven times.