# US 10,872,977 B2 · Diffused tip extension transistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,977 B2 - Document ID: US10872977B2 - Status: Granted - Kind: B2 - Application number: 16/386,197 - Filed: 2019-04-16 - Published: 2019-08-08 - Granted: 2020-12-22 - Earliest claimed: 2019-04-16 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Pratik A. Patel; Mark Y. Liu; Jami A. Wiedemer; Paul A. Packan - Web page: https://patentgrep.com/patent/US10872977B2 ## CPC - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates} - H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/80: characterised by the materials - H10D 62/82: Heterojunctions - H10P 32/1406: {by ion implantation} - H10P 32/171: {being group IV material} - H10P 95/90: Thermal treatments, e.g. annealing or sintering - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant. ## Claims ### Claim 1 An apparatus comprising: a gate electrode transversing a fin extending from a substrate; semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, the semiconductor material filled openings and the fin comprising a same semiconductor material; and a sidewall spacer on each side of the opposite sides of the gate electrode, wherein a portion of the fin underlying the sidewall spacer comprises a dopant, wherein the portion of the fin has a same dopant concentration at a bottom of the fin, at a top of the fin, and along a height of the fin between the bottom of the fin and the top of the fin. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the dopant comprises an N-type dopant. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the dopant is phosphorous. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the semiconductor material is silicon. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the semiconductor filled openings extend a depth of the fin. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the semiconductor filled openings extend a distance greater than depth of the fin. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the semiconductor filled openings extend a distance less than a depth of the fin. ### Claim 8 An apparatus comprising: a gate electrode transversing a fin extending from a substrate; semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, the semiconductor material filled openings and the fin comprising a same semiconductor material, wherein a portion of the fin laterally adjacent to the semiconductor material filled openings comprises a dopant, wherein the portion of the fin has a same dopant concentration at a bottom of the fin, at a top of the fin, and along a height of the fin between the bottom of the fin and the top of the fin. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the dopant comprises an N-type dopant. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein the dopant is phosphorous. ### Claim 11 (depends on 8) The apparatus of claim 8, wherein the semiconductor material is silicon. ### Claim 12 (depends on 8) The apparatus of claim 8, wherein the semiconductor filled openings extend a depth of the fin. ### Claim 13 (depends on 8) The apparatus of claim 8, wherein the semiconductor filled openings extend a distance greater than depth of the fin. ### Claim 14 (depends on 8) The apparatus of claim 8, wherein the semiconductor filled openings extend a distance less than a depth of the fin. ### Claim 15 A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a gate electrode transversing a fin extending from a substrate; semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, the semiconductor material filled openings and the fin comprising a same semiconductor material; and a sidewall spacer on each side of the opposite sides of the gate electrode, wherein a portion of the fin underlying the sidewall spacer comprises a dopant, wherein the portion of the fin has a same dopant concentration at a bottom of the fin, at a top of the fin, and along a height of the fin between the bottom of the fin and the top of the fin. ### Claim 16 (depends on 15) The computing device of claim 15, further comprising: a memory coupled to the board. ### Claim 17 (depends on 15) The computing device of claim 15, further comprising: a communication chip coupled to the board. ### Claim 18 (depends on 15) The computing device of claim 15, further comprising: a camera coupled to the board. ### Claim 19 (depends on 15) The computing device of claim 15, further comprising: a battery coupled to the board. ### Claim 20 (depends on 15) The computing device of claim 15, further comprising: an antenna coupled to the board.