# US 10,872,975 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,975 B2 - Document ID: US10872975B2 - Status: Granted - Kind: B2 - Application number: 16/254,892 - Filed: 2019-01-23 - Published: 2020-02-13 - Granted: 2020-12-22 - Earliest claimed: 2018-08-08 - Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation - Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation - Inventors: Hiroaki Katou - Web page: https://patentgrep.com/patent/US10872975B2 ## CPC - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 64/01: Manufacture or treatment - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D 30/699: {having the gate at least partly formed in a trench} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, and a second electrode. The gate electrode includes a first portion and a second portion. The first portion opposes the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region in a first direction perpendicular to a second direction from the first electrode toward the first semiconductor region. The second portion is arranged with the first portion in a third direction perpendicular to the first and first directions. The second portion opposes the second semiconductor region in the first direction. A lower end of the second portion is positioned higher than an interface between the first semiconductor region and the second semiconductor region. ## Claims ### Claim 1 A semiconductor device, comprising: a first electrode; a first semiconductor region provided on the first electrode, the first semiconductor region being of a first conductivity type; a second semiconductor region provided on the first semiconductor region, the second semiconductor region being of a second conductivity type; a third semiconductor region provided on a portion of the second semiconductor region, the third semiconductor region being of the first conductivity type; a gate electrode including a first portion opposing the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region in a first direction with a gate insulating portion interposed, the first direction being perpendicular to a second direction from the first electrode toward the first semiconductor region, and a second portion arranged with the first portion in a third direction perpendicular to the first direction and the second direction, the second portion opposing the second semiconductor region in the first direction with the gate insulating portion interposed, a lower end of the second portion being positioned higher than an interface between the first semiconductor region and the second semiconductor region; and a second electrode provided on the second semiconductor region and the third semiconductor region, the second electrode being electrically connected to the second semiconductor region and the third semiconductor region; wherein a plurality of the first portions and a plurality of the second portions are provided, and the plurality of first portions and the plurality of second portions are provided alternately in the third direction. ### Claim 2 (depends on 1) The device according to claim 1, further comprising a fourth semiconductor region provided on another portion of the second semiconductor region, the fourth semiconductor region being of the second conductivity type, an impurity concentration of the second conductivity type in the fourth semiconductor region being higher than an impurity concentration of the second conductivity type in the second semiconductor region. ### Claim 3 (depends on 2) The device according to claim 2, wherein the fourth semiconductor region is arranged with the third semiconductor region in the third direction, and the second portion opposes the fourth semiconductor region in the first direction with the gate insulating portion interposed. ### Claim 4 (depends on 1) The device according to claim 1, wherein a length in the third direction of the second portion is not less than 0.5 times and not more than 30 times a length in the third direction of the first portion. ### Claim 5 (depends on 1) The device according to claim 1, further comprising a first conductive portion provided inside the first semiconductor region with a first insulating portion interposed, the first conductive portion being electrically connected to the second electrode, the gate electrode being provided on the first conductive portion with a second insulating portion interposed. ### Claim 6 (depends on 5) The device according to claim 5, wherein a distance between the second portion and the first conductive portion is longer than a distance between the first portion and the first conductive portion. ### Claim 7 (depends on 5) The device according to claim 5, wherein a concentration of boron or phosphorus of the second insulating portion is higher than a concentration of boron or phosphorus of the first insulating portion. ### Claim 8 A semiconductor device, comprising: a first electrode; a first semiconductor region provided on the first electrode, the first semiconductor region being of a first conductivity type; a second semiconductor region provided on the first semiconductor region, the second semiconductor region being of a second conductivity type; a third semiconductor region provided on a portion of the second semiconductor region, the third semiconductor region being of the first conductivity type; a gate electrode including a first portion opposing the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region in a first direction with a gate insulating portion interposed, the first direction being perpendicular to a second direction from the first electrode toward the first semiconductor region, and a second portion arranged with the first portion in a third direction perpendicular to the first direction and the second direction, the second portion opposing the second semiconductor region in the first direction with the gate insulating portion interposed, an upper end of the second portion being positioned lower than an upper end of the first portion; and a second electrode provided on the second semiconductor region and the third semiconductor region, the second electrode being electrically connected to the second semiconductor region and the third semiconductor region; wherein a plurality of the first portions and a plurality of the second portions are provided, and the plurality of first portions and the plurality of second portions are provided alternately in the third direction. ### Claim 9 (depends on 8) The device according to claim 8, wherein a lower end of the second portion is positioned higher than an interface between the first semiconductor region and the second semiconductor region. ### Claim 10 (depends on 8) The device according to claim 8, wherein the upper end of the second portion is positioned lower than an interface between the second semiconductor region and the third semiconductor region. ### Claim 11 (depends on 8) The device according to claim 8, further comprising a fourth semiconductor region provided on another portion of the second semiconductor region, the fourth semiconductor region being of the second conductivity type, an impurity concentration of the second conductivity type in the fourth semiconductor region being higher than an impurity concentration of the second conductivity type in the second semiconductor region. ### Claim 12 (depends on 11) The device according to claim 11, wherein the fourth semiconductor region is arranged with the third semiconductor region in the third direction, and a position in the third direction of at least a portion of the second portion is the same as a position in the third direction of at least a portion of the fourth semiconductor region.