# US 10,872,970 B2 · Source and drain formation technique for fin-like field effect transistor

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- Number: US 10,872,970 B2
- Document ID: US10872970B2
- Status: Granted
- Kind: B2
- Application number: 16/587,754
- Filed: 2019-09-30
- Published: 2020-01-30
- Granted: 2020-12-22
- Earliest claimed: 2016-12-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun Hsiung Tsai; Kuo-Feng Yu; Ziwei Fang
- Web page: https://patentgrep.com/patent/US10872970B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/834: further characterised by the dopants
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 32/1408: {from or through or into an external applied layer, e.g. photoresist or nitride layers}
- H10P 32/1414: {the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon}
- H10P 32/171: {being group IV material}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Source and drain formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, wherein the fin structure include a channel region disposed between a source region and a drain region; forming a gate structure over the channel region of the fin structure; forming a solid phase diffusion (SPD) layer over the source region and the drain region of the fin structure; and performing a microwave annealing (MWA) process to diffuse a dopant from the SPD layer into the source region and the drain region of fin structure. In some implementations, the SPD layer is disposed over the fin structure, such that the dopant diffuses laterally and vertically into the source region and the drain region to form heavily doped source/drain features.

## Claims

### Claim 1

A method comprising:
forming a semiconductor fin structure on a substrate;
forming a first gate structure over the fin structure, wherein the first gate structure includes a first gate electrode;
after forming the first gate structure over the fin structure, forming a doped layer along a sidewall and a top surface of the fin structure, the top surface facing away from the substrate and interfacing with the sidewall;
performing a microwave annealing (MWA) process to laterally and vertically diffuse a dopant from the doped layer into the fin structure;
removing the first gate electrode to form a trench after the performing of MWA process; and
forming a second gate electrode in the trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein a dopant feature is formed in the fin structure by the performing of the MWA process to laterally and vertically diffuse the dopant from the doped layer into the fin structure, and
wherein the dopant feature has a uniform doping concentration.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming of the doped layer along the sidewall and the top surface of the fin structure includes performing an epitaxially growing process to form the doped layer along the sidewall and the top surface of the fin structure.

### Claim 4 (depends on 3)

The method of claim 3, wherein the forming of the doped layer along the sidewall and the top surface of the fin structure further includes introducing the dopant into the epitaxially growing process.

### Claim 5 (depends on 1)

The method of claim 1, wherein the MWA process is performed with a temperature in a range from about 500° C. to about 750° C.

### Claim 6

A method comprising:
forming a fin structure on a substrate, the fin structure including a first sidewall and an opposing second sidewall, wherein a first portion of a dielectric isolation feature is disposed along the first sidewall of the fin structure and a second portion of the dielectric isolation feature is disposed along the second sidewall of the fin structure;
forming a doped layer along the first sidewall, the second sidewall and a top surface of the fin structure, the top surface of the fin structure facing away from the substrate and extending between the first sidewall and the second sidewall of the fin structure; and
performing a microwave annealing (MWA) process to laterally and vertically diffuse a dopant from the doped layer into the fin structure thereby forming a doped feature in the fin structure, wherein the doped feature extends within the fin structure between the first portion of the dielectric isolation feature and the second portion of the dielectric isolation feature.

### Claim 7 (depends on 6)

The method of claim 6, wherein the doped feature has the dopant at a concentration ranging from about 1×1021 cm−3 to about 4×1021 cm−3.

### Claim 8 (depends on 6)

The method of claim 6, wherein the doped feature extends within the fin structure below a top surface of the first portion of the dielectric isolation feature.

### Claim 9 (depends on 6)

The method of claim 6, wherein the MWA process is performed with a temperature in a range from about 500° C. to about 750° C., a power in a range from about 8 kW to about 18 kW, and a time of about 150 seconds to about 300 seconds.

### Claim 10 (depends on 6)

The method of claim 6, wherein the forming of the doped layer along the first sidewall, the second sidewall and the top surface of the fin structure includes forming a first portion of the doped layer over a source region of the fin structure and a second portion of the doped layer over a drain region of the fin structure.

### Claim 11 (depends on 10)

The method of claim 10, wherein the doped layer does not extend continuously from the first portion of the doped layer to the second portion of the doped layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein the first portion of the doped layer includes the dopant at a first concentration and the second portion of the doped layer includes the dopant at a second concentration that is different from the first concentration.

### Claim 13

A method comprising:
forming a semiconductor fin structure on a substrate;
forming a doped layer along a sidewall and a top surface of the fin structure, the top surface facing away from the substrate;
performing a microwave annealing (MWA) process to laterally and vertically diffuse a dopant from the doped layer into the fin structure thereby forming a uniformly doped feature in the fin structure;
forming a gate dielectric layer on the fin structure after the performing of the MWA process; and
forming a gate electrode layer on the gate dielectric layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the doped layer includes a semiconductor material.

### Claim 15 (depends on 13)

The method of claim 13, wherein the forming of the doped layer along the sidewall and the top surface of the fin structure includes forming a first portion of the doped layer over a first source/drain region of the fin structure and a second portion of the doped layer over a second source/drain region of the fin structure.

### Claim 16 (depends on 15)

The method of claim 15, wherein a channel region of the fin structure is disposed between the first source/drain region of the fin structure and the second source/drain region of the fin structure, and
wherein the channel region of the fin structure is free of the doped layer after the forming of the doped layer along the sidewall and the top surface of the fin structure.

### Claim 17 (depends on 13)

The method of claim 13, wherein the MWA process is performed with a temperature in a range from about 500° C. to about 750° C. and a time of about 150 seconds to about 300 seconds.

### Claim 18 (depends on 13)

The method of claim 13, wherein the sidewall of the fin structure is a first sidewall and the fin structure further includes an opposing second sidewall,
wherein a first portion of a dielectric isolation feature is disposed along the first sidewall of the fin structure and a second portion of the dielectric isolation feature is disposed along the second sidewall of the fin structure, and
wherein the uniformly doped feature extends within the fin structure between the first portion of the dielectric isolation feature and the second portion of the dielectric isolation feature after the performing of the MWA process.

### Claim 19 (depends on 1)

The method of claim 1, wherein the forming of the doped layer along the sidewall and the top surface of the fin structure includes forming the doped layer on the fin structure on opposite sides of the first gate structure.

### Claim 20 (depends on 1)

The method of claim 1, wherein a dopant feature is formed in the fin structure by the performing of the MWA process to laterally and vertically diffuse the dopant from the doped layer into the fin structure,
wherein the sidewall of the fin structure is a first sidewall and the fin structure further includes an opposing second sidewall,
wherein a first portion of a dielectric isolation feature is disposed along the first sidewall of the fin structure and a second portion of the dielectric isolation feature is disposed along the second sidewall of the fin structure, and
wherein the doped feature extends within the fin structure between the first portion of the dielectric isolation feature and the second portion of the dielectric isolation feature after the performing of the MWA process.