# US 10,872,968 B2 · Semiconductor device

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- Number: US 10,872,968 B2
- Document ID: US10872968B2
- Status: Granted
- Kind: B2
- Application number: 15/959,298
- Filed: 2018-04-23
- Published: 2018-08-23
- Granted: 2020-12-22
- Earliest claimed: 2015-12-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Che-Cheng Chang; Chih-Han Lin; Horng-Huei Tseng
- Web page: https://patentgrep.com/patent/US10872968B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 14/6329: {using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including a first fin field effect transistor and a second fin field effect transistor is provided. The first fin field effect transistor includes a first semiconductor channel, a first gate overlapped with the first semiconductor channel, a first dielectric layer disposed between the first semiconductor channel and the first gate, and a pair of first spacers disposed on sidewalls of the first gate. The second fin field effect transistor includes a second semiconductor channel, a second gate overlapped with the second semiconductor channel, a second dielectric layer disposed between the second semiconductor channel and the second gate, and a pair of second spacers. The second dielectric layer further extends between the second gate and the pair of second spacers, the first dielectric layer is thinner than the second dielectric layer, and a width of the first gate is smaller than that of the second gate.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate comprising insulators and a semiconductor fin between the insulators;
a first dielectric layer partially covering the insulators and comprising first dielectric portions, a second dielectric portion, and third dielectric portions;
a pair of first spacers, wherein the first dielectric portions cover first portions of the semiconductor fin, and the first dielectric portions are covered by the pair of first spacers;
a first gate disposed between the pair of first spacers, wherein the second dielectric portion of the first dielectric layer extends between the first dielectric portions, the second dielectric portion covers a second portion of the semiconductor fin, the second portion of the semiconductor fin is located between the first portions of the semiconductor fin, and the second portion of the semiconductor fin is covered by the first gate;
a pair of second spacers, wherein the third dielectric portions cover third portions of the semiconductor fin, and the third dielectric portions are covered by the pair of second spacers;
a second dielectric layer disposed between the pair of second spacers, wherein the second dielectric layer is in contact with sidewalls of the pair of second spacers and a fourth portion of the semiconductor fin, the fourth portion of the semiconductor fin is located between the third portions of the semiconductor fin, and the first dielectric layer is thinner than the second dielectric layer; and
a second gate disposed on the second dielectric layer and between the pair of second spacers, wherein a width of the first gate is smaller than a width of the second gate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the first dielectric layer ranges from 0.2 nm to 5 nm and a thickness of the second dielectric layer ranges from 5 nm to 50 nm.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the width of the first gate ranges from 5 nm to 50 nm and the width of the second gate is greater than 50 nm.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric layer is in contact with the third dielectric portions.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the width of the second gate is smaller than a gap between the pair of second spacers.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the width of the first gate is substantially equal to a gap between the pair of first spacers.

### Claim 7

A semiconductor device, comprising:
a first fin field effect transistor comprising a first semiconductor fin, a first gate overlapped with the first semiconductor fin, a first dielectric layer, and a pair of first spacers disposed on sidewalls of the first gate, wherein the first dielectric layer comprises first dielectric portions covered by the pair of first spacers, the first dielectric portions cover first portions of the semiconductor fin, the first dielectric layer comprises a second dielectric portion covered by the first gate, the second dielectric portion covers a second portion of the semiconductor fin, and the second portion of the semiconductor fin is located between the first portions of the semiconductor fin; and
a second fin field effect transistor comprising a second semiconductor fin, a second gate overlapped with the second semiconductor fin, a second dielectric layer, and a pair of second spacers, wherein the first dielectric layer comprises third dielectric portions covered by the pair of second spacers, the third dielectric portions of the first dielectric layer cover third portions of the semiconductor fin, the second dielectric layer covers a fourth portion of the semiconductor fin, and the second dielectric layer is between the second gate and the pair of second spacers, the fourth portion of the semiconductor fin is located between the third portions of the semiconductor fin, the first dielectric layer is thinner than the second dielectric layer, and a width of the first gate is smaller than that of the second gate.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein a thickness of the first dielectric layer ranges from 0.2 nm to 5 nm and a thickness of the second dielectric layer ranges from 5 nm to 50 nm.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the width of the first gate ranges from 5 nm to 50 nm and the width of the second gate is greater than 50 nm.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, wherein a channel length of the first semiconductor channel ranges from 5 nm to 50 nm and a channel length of the second semiconductor channel is greater than 50 nm.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, wherein a channel length of the first semiconductor channel is smaller than that of the second semiconductor channel.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, wherein the width of the first gate is substantially equal to a gap between the pair of first spacers.

### Claim 13 (depends on 7)

The semiconductor device of claim 7, wherein the width of the second gate is smaller than a gap between the pair of second spacers.

### Claim 14

A semiconductor device, comprising:
a semiconductor fin comprising a first channel portion and a second channel portion;
a first gate overlapped with the first channel portion of the semiconductor fin;
a first dielectric layer covering the first channel portion of the semiconductor fin, the first dielectric layer being between the first gate and the first channel portion of the semiconductor fin;
a pair of first spacers disposed on the first dielectric layer and covering sidewalls of the first gate, wherein first dielectric portions of the first dielectric layer are covered by the pair of first spacers;
a second dielectric layer covering the second channel portion of the semiconductor fin, the second channel portion being uncovered by the first dielectric layer, and the first dielectric layer being thinner than the second dielectric layer;
a second gate disposed on the second dielectric layer and overlapped with the second channel portion of the semiconductor fin, a width of the first gate being smaller than that of the second gate; and
a pair of second spacers disposed on the first dielectric layer, wherein the second dielectric layer is disposed between the pair of second spacers to space apart the second gate from the pair of second spacers, second dielectric portions of the first dielectric layer are covered by the pair of second spacers, and the second dielectric layer is in contact with the second dielectric portions of the first dielectric layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein a thickness of the first dielectric layer ranges from 0.2 nm to 5 nm and a thickness of the second dielectric layer ranges from 5 nm to 50 nm.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the width of the first gate ranges from 5 nm to 50 nm and the width of the second gate is greater than 50 nm.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein a channel length of the first channel portion ranges from 5 nm to 50 nm and a channel length of the second channel portion is greater than 50 nm.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein a channel length of the first channel portion is smaller than that of the second channel portion.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, wherein the width of the first gate is substantially equal to a gap between the pair of first spacers.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, wherein the width of the second gate is smaller than a gap between the pair of second spacers.