# US 10,872,967 B2 · Manufacturing method of semiconductor device

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- Number: US 10,872,967 B2
- Document ID: US10872967B2
- Status: Granted
- Kind: B2
- Application number: 16/521,572
- Filed: 2019-07-24
- Published: 2020-11-26
- Granted: 2020-12-22
- Earliest claimed: 2019-05-24
- Assignees: Glc Semiconductor Group (Cq) Co., Ltd.
- Applicants: Glc Semiconductor Group (Cq) Co., Ltd.
- Inventors: Yi-Chun Shih; Shun-Min Yeh
- Web page: https://patentgrep.com/patent/US10872967B2

## CPC

- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 64/01: Manufacture or treatment
- H10D 64/111: {Field plates}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/685: {being perpendicular to the channel plane}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 62/854: further characterised by the dopants
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A manufacturing method of a semiconductor device includes the following steps. At least one mesa structure is provided. The mesa structure includes a III-V compound semiconductor layer. A passivation layer is formed on the mesa structure. A gate dielectric layer is formed on the passivation layer, and a gate electrode is formed on the gate dielectric layer. An etching process is performed to the gate dielectric layer for thinning the gate dielectric layer before the step of forming the gate electrode. The thickness of the gate dielectric layer may be modified by the etching process, and the electrical performance of the semiconductor device may be enhanced accordingly.

## Claims

### Claim 1

A manufacturing method of a semiconductor device, comprising:
providing at least one mesa structure, wherein the at least one mesa structure comprises a III-V compound semiconductor layer;
forming a passivation layer on the at least one mesa structure;
forming a gate dielectric layer on the passivation layer;
forming a gate electrode on the gate dielectric layer; and
performing an etching process to the gate dielectric layer for thinning the gate dielectric layer before forming the gate electrode, wherein a thickness of the gate dielectric layer is greater than a thickness of the passivation layer before the etching process, and the thickness of the gate dielectric layer is less than the thickness of the passivation layer after the etching process.

### Claim 2 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, further comprising:
forming recesses in the at least one mesa structure, wherein at least a part of the gate electrode is formed in the recesses.

### Claim 3 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the providing the at least one mesa structure comprises providing a plurality of the mesa structures, and the manufacturing method of the semiconductor device further comprises:
forming an isolation structure between the mesa structures, wherein the passivation layer is further formed on the isolation structure.

### Claim 4 (depends on 3)

The manufacturing method of the semiconductor device according to claim 3, further comprising:
forming a recess in at least one of the mesa structures, wherein at least a part of the gate electrode is formed in recess, and the isolation structure is formed before the step of forming the recess.

### Claim 5 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, further comprising:
forming a recess in the at least one mesa structure, wherein at least a part of the gate electrode is formed in the recess.

### Claim 6 (depends on 5)

The manufacturing method of the semiconductor device according to claim 5, wherein the passivation layer and the gate dielectric layer are formed after the step of forming the recess, and the passivation layer and the gate dielectric layer are partially formed in the recess.

### Claim 7 (depends on 5)

The manufacturing method of the semiconductor device according to claim 5, wherein the at least one mesa structure further comprises a nitride layer disposed on the III-V compound semiconductor layer, and the recess is partially formed in the nitride layer.

### Claim 8 (depends on 7)

The manufacturing method of the semiconductor device according to claim 7, wherein a part of the recess is further formed in the III-V compound semiconductor layer.

### Claim 9 (depends on 5)

The manufacturing method of the semiconductor device according to claim 5, wherein the passivation layer comprises a first passivation layer and a spacer, and methods of forming the passivation layer and the recess comprises:
forming the first passivation layer on the at least one mesa structure;
forming an opening in the first passivation layer and forming the spacer on a sidewall of the opening; and
etching the at least one mesa structure with the spacer as a mask for forming the recess.

### Claim 10 (depends on 9)

The manufacturing method of the semiconductor device according to claim 9, wherein the passivation layer further comprises a second passivation layer, the second passivation layer is formed after the step of forming the recess, and at least a part of the second passivation layer is formed in the recess.

### Claim 11 (depends on 5)

The manufacturing method of the semiconductor device according to claim 5, further comprising:
forming a fluorine doped region in the at least one mesa structure under the recess.

### Claim 12 (depends on 11)

The manufacturing method of the semiconductor device according to claim 11, wherein at least a part of the fluorine doped region is located in the III-V compound semiconductor layer.

### Claim 13 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, further comprising:
forming a source electrode and a drain electrode at two sides of the gate electrode in a horizontal direction respectively, wherein the source electrode is partially formed in the at least one mesa structure, and the drain electrode is partially formed in the at least one mesa structure.

### Claim 14 (depends on 13)

The manufacturing method of the semiconductor device according to claim 13, wherein the source electrode and the drain electrode penetrate the gate dielectric layer and the passivation layer on the at least one mesa structure.

### Claim 15 (depends on 13)

The manufacturing method of the semiconductor device according to claim 13, wherein the at least one mesa structure further comprises a nitride layer disposed on the III-V compound semiconductor layer, and the source electrode and the drain electrode are partially formed in the nitride layer.

### Claim 16 (depends on 15)

The manufacturing method of the semiconductor device according to claim 15, wherein the source electrode and the drain electrode are further partially formed in the III-V compound semiconductor layer.

### Claim 17 (depends on 13)

The manufacturing method of the semiconductor device according to claim 13, further comprising:
forming an auxiliary electrode on the at least one mesa structure between the gate electrode and the drain electrode.

### Claim 18 (depends on 17)

The manufacturing method of the semiconductor device according to claim 17, wherein the auxiliary electrode is electrically floating.

### Claim 19 (depends on 17)

The manufacturing method of the semiconductor device according to claim 17, wherein the auxiliary electrode is electrically connected with the source electrode.