# US 10,872,965 B2 · Method of forming semiconductor structure

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- Number: US 10,872,965 B2
- Document ID: US10872965B2
- Status: Granted
- Kind: B2
- Application number: 16/914,940
- Filed: 2020-06-29
- Published: 2020-10-15
- Granted: 2020-12-22
- Earliest claimed: 2018-07-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chang-Yin Chen; Che-Cheng Chang; Chih-Han Lin
- Web page: https://patentgrep.com/patent/US10872965B2

## CPC

- H10D 64/679: {comprising air gaps}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10P 52/403: {of conductive or resistive materials}
- H10P 70/23: {during, before or after processing of insulating materials}
- H10P 76/2041: {Photolithographic processes}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 95/062: {involving a dielectric removal step}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor structure includes forming a dummy gate feature over a semiconductive fin; forming a first spacer around the dummy gate feature and a second spacer around the first spacer; replacing the dummy gate feature with a metal gate feature; after replacing the dummy gate feature with the metal gate feature, partially removing the second spacer such that a top of the second spacer is lower than a top of the first spacer; and depositing a capping layer over and in contact with the metal gate feature and the first spacer.

## Claims

### Claim 1

A method, comprising:
forming a dummy gate feature over a semiconductive fin;
forming a first spacer around the dummy gate feature and a second spacer around the first spacer;
replacing the dummy gate feature with a metal gate feature;
after replacing the dummy gate feature with the metal gate feature, partially removing the second spacer such that a top of the second spacer is lower than a top of the first spacer; and
depositing a capping layer over and in contact with the metal gate feature and the first spacer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a third spacer around the second spacer before replacing the dummy gate feature with the metal gate feature.

### Claim 3 (depends on 2)

The method of claim 2, wherein partially removing the second spacer is performed such that a bottom of the third spacer is at least partially exposed after partially removing the second spacer.

### Claim 4 (depends on 2)

The method of claim 2, wherein depositing the capping layer is performed such that the capping layer has a first portion extending along a top of the metal gate feature, the top of the first spacer and a top of the third spacer and a second portion extending downwards from a bottom of the first portion and sandwitched between the first spacer and the third spacer.

### Claim 5 (depends on 1)

The method of claim 1, wherein depositing the capping layer is performed such that a bottom of the capping layer is lower than the top of the first spacer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming the first spacer is performed such that the first spacer has a first portion extending along sidewalls of the dummy gate feature and a second portion extending laterally from a bottom of the first portion, wherein partially removing the second spacer is performed such that a top of the second portion of the first spacer is at least partially exposed after partially removing the second spacer.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming a third spacer around the first spacer, wherein forming the second spacer is performed such that the second spacer is formed around the third spacer.

### Claim 8 (depends on 7)

The method of claim 7, wherein partially removing the second spacer is performed such that the top of the second spacer is lower than a top of the third spacer after partially removing the second spacer.

### Claim 9 (depends on 7)

The method of claim 7, where depositing the capping layer is performed such that the capping layer is in contact with the third spacer.

### Claim 10

A method, comprising:
forming a dummy gate feature over a semiconductive fin;
forming a first spacer around the dummy gate feature;
depositing a contact etch stop layer over the dummy gate feature and the first spacer;
depositing an interlayer dielectric layer over the contact etch stop layer;
removing a portion of the interlayer dielectric layer and a first portion of the contact etch stop layer to expose a top of the dummy gate feature;
replacing the dummy gate feature with a metal gate feature; and
after replacing the dummy gate feature with the metal gate feature, etching the contact etch stop layer to form a void between the first spacer and the interlayer dielectric layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the interlayer dielectric layer has a sidewall facing the metal gate feature, and etching the contact etch stop layer is performed such that the sidewall of the interlayer dielectric layer is at least partially exposed after etching the contact etch stop layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein the interlayer dielectric layer has a sidewall facing the metal gate feature, and etching the contact etch stop layer is performed such that the contact etch stop layer has a second portion extending along the sidewall of the interlayer dielectric layer after etching the contact etch stop layer.

### Claim 13 (depends on 10)

The method of claim 10, further comprising forming a second spacer around the first spacer, wherein when the contact etch stop layer is etched to form the void, the second spacer is also etched.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming a third spacer around the first spacer, wherein forming the second spacer is performed such that the second spacer is formed around the third spacer.

### Claim 15

A method, comprising:
forming a dummy gate feature over a channel region of a semiconductive fin;
forming a first spacer around the dummy gate feature and a second spacer around the first spacer;
forming source and drain features in the semiconductive fin;
forming an interlayer dielectric layer around the dummy gate feature and over the source and drain features;
replacing the dummy gate feature with a metal gate feature;
etching the second spacer between the first spacer and the interlayer dielectric layer; and
after etching the second spacer, depositing a capping layer over and in contact with the first spacer and the interlayer dielectric layer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming a third spacer around the second spacer before forming the source and drain features.

### Claim 17 (depends on 15)

The method of claim 15, wherein etching the second spacer is performed such that a top of the second spacer is higher than a top of the source feature after etching the second spacer.

### Claim 18 (depends on 15)

The method of claim 15, wherein depositing the capping layer is performed such that the capping layer has a portion between the first spacer and the interlayer dielectric layer, and said portion of the capping layer between the first spacer and the interlayer dielectric layer has a bottom lower than a top of the interlayer dielectric layer.

### Claim 19 (depends on 15)

The method of claim 15, wherein etching the second spacer is performed such that a sidewall of the first spacer is at least partially exposed after etching the second spacer.

### Claim 20 (depends on 15)

The method of claim 15, wherein depositing the capping layer is performed such that the capping layer is spaced apart from the second spacer.