# US 10,872,961 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 10,872,961 B2
- Document ID: US10872961B2
- Status: Granted
- Kind: B2
- Application number: 16/102,468
- Filed: 2018-08-13
- Published: 2020-02-13
- Granted: 2020-12-22
- Earliest claimed: 2018-08-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Han-Pin Chung
- Web page: https://patentgrep.com/patent/US10872961B2

## CPC

- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins on a substrate. A liner layer is deposited on the semiconductor fins and on the substrate conformally. The semiconductor fins are patterned to form a plurality of active regions on the substrate after the liner layer is deposited.

## Claims

### Claim 1

A method comprising:
forming a first semiconductive fin on a substrate;
depositing a liner layer on the first semiconductive fin and on the substrate conformally;
after depositing the liner layer, etching a first portion of the liner layer and a portion of the first semiconductive fin to separate the first semiconductive fin into second and third semiconductive fins on the substrate, wherein after etching the first semiconductive fin, each of the second and third semiconductive fins have first and second sidewalls that remain covered by the liner layer, and an end sidewall exposed by the liner layer;
forming an isolation layer on the end sidewall of each of the second and third semiconductive fins and on the liner layer so that it extends along the first and second sidewalls of each of the second and third semiconductive fins;
recessing the isolation layer, such that a top portion of the end sidewall of each of the second and third semiconductive fins is exposed and an isolation structure is formed between bottom portions of the second and third semiconductive fins;
after recessing the isolation layer, forming a first dummy gate structure and a second dummy gate structure respectively on a portion of the second semiconductive fin and a portion of the third semiconductive fin; and
replacing the first and second dummy gate structures respectively with first and second metal gate structures.

### Claim 2 (depends on 1)

The method of claim 1, wherein etching the first semiconductive fin comprises:
forming a cut opening cutting through the first semiconductive fin.

### Claim 3 (depends on 1)

The method of claim 1, wherein etching the first semiconductive fin comprises:
forming an end-to-end cut opening between the second and third semiconductive fins.

### Claim 4 (depends on 1)

The method of claim 1, wherein the end sidewall of the second semiconductive fin faces the end sidewall of the third semiconductive fin.

### Claim 5 (depends on 1)

The method of claim 1, wherein the end sidewall of each of the second and third semiconductive fins interconnects the first and second sidewalls of each of the second and third semiconductive fins.

### Claim 6 (depends on 1)

The method at claim 1, further comprising:
removing a second portion of the liner layer above the isolation structure such that a third portion of the liner layer remains between the bottom portions of the second and third semiconductive fins and the isolation structure.

### Claim 7 (depends on 1)

The method of claim 1; wherein the isolation layer directly contacts the exposed end sidewalls of the second and third semiconductive fins.

### Claim 8 (depends on 6)

The method of claim 6, wherein a topmost surface of the third portion of the liner layer is level with a topmost surface of the isolation structure.

### Claim 9

A method comprising:
depositing a liner layer on a first semiconductive fin and on a substrate conformally;
after depositing the liner layer, removing a portion of the first semiconductive fin and a portion of the liner layer thereon, such that the first semiconductive fin is separated into second and third semiconductive fins, wherein the second and third semiconductive fins are end-to-end arranged on the substrate, and after etching the first semiconductive fin, each of the second and third semiconductive fins have first and second sidewalls that remain covered by the liner layer, and a first end sidewall exposed by the liner layer;
depositing a dielectric material on the first end sidewall of each of the second and third semiconductive fins and on the liner layer so that it extends along the first and second sidewalls of each of the second and third semiconductive fins; and
recessing the dielectric material, such that a portion of the first end sidewall of each of the second and third semiconductive fins is exposed and an isolation structure is formed between bottom portions of the second and third semiconductive fins.

### Claim 10 (depends on 9)

The method of claim 9, wherein a second end sidewall of the second semiconductive fin is covered by the liner layer, after the portion of the first semiconductive fin and the portion of the liner layer are removed.

### Claim 11 (depends on 10)

The method of claim 10, wherein depositing the dielectric material is performed such that the dielectric material directly contacts the first end sidewall of the second semiconductive fin.

### Claim 12 (depends on 10)

The method of claim 10, wherein depositing the dielectric material is performed such that the liner layer remains between the dielectric material and the second end sidewall of the second semiconductive fin.

### Claim 13 (depends on 10)

The method of claim 10, wherein a second end sidewall of the third semiconductive fin is covered by the liner layer, after the portion of the first semiconductive fin and the portion of the liner layer are removed.

### Claim 14 (depends on 13)

The method of claim 13, wherein depositing the dielectric material is performed such that the dielectric material directly contacts the first end sidewall of the second semiconductive fin and the first end sidewall of the third semiconductive fin.

### Claim 15

A method comprising:
forming a first semiconductive fin on a substrate, wherein the first semiconductive fin has a top surface and sidewalls;
depositing a liner layer on the top surface and the sidewalls of the first semiconductive fin;
etching a first portion of the liner layer and a portion of the first semiconductive fin, such that the first semiconductive fin is separated into second and third semiconductive fins, and second and third portions of the liner layer remain respectively on first and second sidewalls of the second and third semiconductive fins and the liner layer exposes an end sidewall of the second and third semiconductive fins;
depositing a dielectric material on the end sidewall of each of the second and third semiconductive fins and on the second and third portions of the liner layer so that it extends along the first and second sidewalls of each of the second and third semiconductive fins; and
after etching the first portion of the liner layer and the portion of the first semiconductive fin, etching an upper portion of the dielectric material and upper sub-portions of the second and third portions of the liner layer, such that upper portions of the end sidewall of each of the second and third semiconductive fins are exposed.

### Claim 16 (depends on 15)

The method of claim 15, wherein depositing the liner layer comprises:
depositing an oxide layer on the top surface and the sidewalls of the first semiconductive fin; and
depositing a nitride layer on the oxide layer.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
forming a gate electrode extending across the second semiconductive fin; and
forming a plurality of source/drain structures on the second semiconductive fin and adjacent the gate electrode.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a contact etch stop layer conformally formed on the source/drain structures and in contact with a topmost surface of the liner layer.

### Claim 19 (depends on 15)

The method of claim 15, further comprising forming a first dummy gate structure and a second dummy gate structure respectively across of the second and third semiconductive fins.

### Claim 20 (depends on 19)

The method of claim 19, further comprising replacing the first and second dummy gate structures respectively with first and second metal gate structures.