# US 10,872,960 B2 · Contact architecture for capacitance reduction and satisfactory contact resistance

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- Number: US 10,872,960 B2
- Document ID: US10872960B2
- Status: Granted
- Kind: B2
- Application number: 16/465,489
- Filed: 2016-12-30
- Published: 2020-02-27
- Granted: 2020-12-22
- Earliest claimed: 2016-12-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Rishabh Mehandru; Pratik A. Patel; Thomas T. Troeger; Szuya S. Liao
- Web page: https://patentgrep.com/patent/US10872960B2

## CPC

- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01: Manufacture or treatment
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/679: {comprising air gaps}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3442: {N-type}
- H10P 14/3444: {P-type}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 50/642: {Chemical etching}
- H10P 95/04: {Planarisation of conductive or resistive materials}
- H10W 20/076: {in via holes or trenches}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

## Claims

### Claim 1

A solid-state device, comprising:
a semiconductor film having a surface;
a first contact member assembled adjacent to a portion of the surface, the first contact member forming a first planar interface with a first dielectric layer in contact with the portion of the surface;
a second dielectric layer assembled adjacently to the first contact member, the second dielectric layer forming a second planar interface with the first contact member, the second planar interface being substantially perpendicular to the first planar interface;
a third dielectric layer assembled adjacently to the second dielectric layer, the third dielectric layer forming a third planar interface with the second dielectric layer, the third planar interface being substantially parallel to the second planar interface;
a conductive interconnect assembled adjacently to the third dielectric layer, the conductive interconnect forming a fourth planar interface with the third dielectric layer;
a second contact member embedded in the semiconductor film, the second contact member forming a fifth planar interface with the conductive interconnect, the planar interface registered with the surface; and
a carrier-doped epitaxial layer forming a non-planar interface with the second contact member.

### Claim 2 (depends on 1)

The solid-state device of claim 1, wherein the second dielectric layer comprises at least one of a silicon oxide or a high-k dielectric, and
wherein the third dielectric layer comprises a low-k material.

### Claim 3 (depends on 1)

The solid-state device of claim 1, wherein the third dielectric layer comprises at least one of silicon dioxide or a low-k material.

### Claim 4 (depends on 1)

The solid-state device of claim 1, wherein the third dielectric layer comprises an air gap.

### Claim 5 (depends on 1)

The solid-state device of claim 1, wherein the second dielectric layer has a thickness in a range from about 0.5 nm to about 10.0 nm.

### Claim 6 (depends on 1)

The solid-state device of claim 1, wherein the third dielectric layer has a thickness in a range from about 0.5 nm to about 10.0 nm.

### Claim 7 (depends on 1)

The solid-state device of claim 1, wherein the second dielectric layer has a first thickness and the third dielectric layer has a second thickness, and wherein the first thickness and the second thickness amount to a total thickness in a range from about 1.0 nm to about 10.0 nm.

### Claim 8 (depends on 1)

The solid-state device of claim 1, wherein the conductive interconnect comprises copper, aluminum, tungsten, titanium, tantalum, silver, gold, palladium, platinum, zinc, nickel, or an alloy of two or more of the foregoing metals.

### Claim 9 (depends on 1)

The solid-state device of claim 1, wherein the first contact member comprises copper, aluminum, tungsten, titanium, tantalum, silver, gold, palladium, platinum, zinc, nickel, or an alloy of two or more of the foregoing metals.

### Claim 10 (depends on 1)

The solid-state device of claim 1, wherein the second contact member comprises copper, aluminum, tungsten, titanium, tantalum, silver, gold, palladium, platinum, zinc, nickel, or an alloy of two or more of the foregoing metals.

### Claim 11 (depends on 1)

The solid-state device of claim 1, wherein the carrier-doped epitaxial layer comprises one of an n-type epitaxial layer or a p-type epitaxial layer.

### Claim 12 (depends on 1)

The solid-state device of claim 1, wherein the semiconductor film comprises silicon, germanium, an alloy of silicon and germanium, a III-V semiconductor compound, or a II-VI semiconductor compound, phosphorous and silicon, or boron and silicon.

### Claim 13 (depends on 11)

The solid-state device of claim 11, wherein the carrier-doped epitaxial layer comprises one of a P-doped epitaxial layer, an As-doped epitaxial layer, a N-doped epitaxial layer; a B-doped epitaxial layer, or an Al-doped epitaxial layer.

### Claim 14

A method for fabricating a solid-state device, comprising:
providing a semiconductor substrate that has a surface, a portion of the surface forming a first interface with a first dielectric layer forming a second interface with a first contact member;
forming a second dielectric layer of a first thickness on a second portion of the surface, the second dielectric layer forming a third interface with the first contact member;
forming a carrier-doped epitaxial layer within the semiconductor substrate; the carrier-doped epitaxial layer assembled as a lining on a surface of a trench in the semiconductor substrate;
forming a second contact member that fills the trench and has a planar surface substantially aligned with the surface, the second contact member extending from a surface of the carrier-doped epitaxial layer to the planar surface, along a direction perpendicular to the surface;
forming a third dielectric layer of a second thickness on a first portion of the planar surface, the third dielectric layer forming a fourth interface with the second dielectric layer; and
forming a conductive interconnect member on a second portion of the planar surface, the conductive interconnect member extending from the planar surface along the direction and forming a fifth interface with the third dielectric layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the forming the second dielectric layer comprises depositing a conformal layer of a high-k dielectric material on the first contact member and the second portion of the surface, the conformal layer having the first thickness, and
removing a portion of the conformal layer.

### Claim 16 (depends on 14)

The method of claim 14, wherein the forming the carrier-doped epitaxial layer comprises etching the semiconductor substrate to form the trench, and
depositing one of an n-type epitaxial layer or ap-type epitaxial layer by means of chemical vapor deposition (CVD).

### Claim 17 (depends on 14)

The method of claim 14, wherein the forming the carrier-doped epitaxial layer comprises forming one of a p-type region by subjecting a third portion of the surface to ion implantation, the formed p-type region embedded in the semiconductor substrate and having a planar surface adjacent to the second portion of the surface, and
etching a portion of the formed p-type region, resulting in a p-type epitaxial layer.

### Claim 18 (depends on 14)

The method of claim 14, wherein the forming the carrier-doped epitaxial layer comprises forming one of an n-type region by subjecting a third portion of the surface to ion implantation, the formed n-type region embedded in the semiconductor substrate and having a planar surface adjacent to the second portion of the surface, and
etching a portion of the formed n-type region, resulting in an n-type epitaxial layer.

### Claim 19 (depends on 14)

The method of claim 14, wherein the forming the second contact member comprises depositing an amount of a conductive material that fills the trench and yields an overburden layer above the surface, and
planarizing the overburden layer to form the planar surface substantially aligned with the surface.

### Claim 20 (depends on 14)

The method of claim 14, wherein the forming the third dielectric layer comprises depositing a conformal layer of a low-k dielectric material on the first contact member, the second dielectric layer, and the planar surface substantially aligned with the surface, the conformal layer having the second thickness, and
removing a portion of the conformal layer, exposing the second portion of the planar surface.

### Claim 21

A solid-state device, comprising:
a semiconductor film having a surface;
a gate contact assembled adjacent to a portion of the surface, the gate contact forming a first interface with a first dielectric layer in contact with the portion of the surface;
a second dielectric layer assembled adjacent to the gate contact, the second dielectric layer forming a second interface with the gate contact;
a third dielectric layer assembled adjacent to the second dielectric layer, the third dielectric layer forming a third interface with the second dielectric layer, the third interface being substantially parallel to the second interface;
a conductive interconnect assembled adjacent to the third dielectric layer, the conductive interconnect forming a fourth interface with the third dielectric layer;
a first contact embedded in the semiconductor film and assembled adjacent to the gate contact, the first contact forming a fifth interface with the conductive interconnect;
a first carrier-doped epitaxial layer forming a non-planar interface with the first contact;
a second contact embedded in the semiconductor film and assembled adjacent to the gate contact; and
a second carrier-doped epitaxial layer forming a non-planar interface with the second contact.

### Claim 22 (depends on 21)

The solid-state device of claim 21, wherein the second dielectric layer comprises at least one of a silicon oxide or a high-k dielectric, and wherein the third dielectric layer comprises a low-k material.

### Claim 23 (depends on 21)

The solid-state device of claim 21, wherein the third dielectric layer comprises at least one of silicon dioxide or a low-k material.

### Claim 24 (depends on 21)

The solid-state device of claim 21, wherein the second dielectric layer has a thickness in a range from about 0.5 nm to about 10.0 nm.

### Claim 25 (depends on 21)

The solid-state device of claim 21, wherein the third dielectric layer has a thickness in a range from about 0.5 nm to about 10.0 nm.