# US 10,872,959 B2 · Semiconductor device and power converter

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- Number: US 10,872,959 B2
- Document ID: US10872959B2
- Status: Granted
- Kind: B2
- Application number: 16/246,594
- Filed: 2019-01-14
- Published: 2019-10-10
- Granted: 2020-12-22
- Earliest claimed: 2018-04-05
- Assignees: Mitsubishi Electric Corporation
- Applicants: Mitsubishi Electric Corporation
- Inventors: Ze Chen
- Web page: https://patentgrep.com/patent/US10872959B2

## CPC

- H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H02M 7/53871: {with automatic control of output voltage or current}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H02P 27/08: with pulse width modulation
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H02P: CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS

## Abstract

A semiconductor device includes gate trenches and dummy gate trenches formed on the upper surface side of a semiconductor substrate, gate electrodes embedded in the gate trenches, dummy gate electrodes embedded in the dummy gate trenches, a channel layer formed in the surface portion on the upper surface side of the semiconductor substrate, a carrier storage layer formed below the channel layer, and a collector layer formed on the lower surface side of the semiconductor substrate. A relationship D4<D1<D3<D2 holds true, where D1 is the depth of the bottoms of the gate electrodes, D2 is the depth of the bottoms of the dummy gate electrodes, D3 is the depth of the bottom of the carrier storage layer, and D4 is the depth of the junction between the channel layer and the carrier storage layer.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
gate trenches formed on an upper surface side of the semiconductor substrate;
gate electrodes embedded in the gate trenches;
a gate insulating film interposed between the gate electrodes and the semiconductor substrate;
a channel layer of a second conductivity type formed in a surface portion on the upper surface side of the semiconductor substrate;
a contact layer of the second conductivity type formed in a surface portion of the channel layer and having a higher peak impurity concentration than the channel layer;
an emitter layer of the first conductivity type formed adjacent to the gate trenches in the surface portion of the channel layer;
a carrier storage layer of the first conductivity type formed below the channel layer;
a collector layer of the second conductivity type formed on a lower surface side of the semiconductor substrate;
a dummy gate trench formed between each two adjacent ones of the gate trenches on the upper surface side of the semiconductor substrate;
dummy gate electrodes embedded in the dummy gate trenches; and
a dummy gate insulating film interposed between the dummy gate electrodes and the semiconductor substrate, wherein
a relationship D4<D1<D3<D2 holds true,
where D1 is a depth of bottoms of the gate electrodes, D2 is a depth of bottoms of the dummy gate electrodes, D3 is a depth of a bottom of the carrier storage layer, and D4 is a depth of a junction between the channel layer and the carrier storage layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
an interval between two adjacent ones of the dummy gate electrodes that sandwich at least one of the gate electrodes therebetween is less than or equal to 15 μm.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
the dummy gate electrodes are electrically connected to the contact layer.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, wherein
the dummy gate electrodes are electrically connected to the contact layer.

### Claim 5 (depends on 1)

A power converter including the semiconductor device according to claim 1, the power converter comprising:
a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device;
a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and
a control circuit to output a control signal for controlling the drive circuit to the drive circuit.

### Claim 6 (depends on 2)

A power converter including the semiconductor device according to claim 2, the power converter comprising:
a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device;
a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and
a control circuit to output a control signal for controlling the drive circuit to the drive circuit.

### Claim 7 (depends on 3)

A power converter including the semiconductor device according to claim 3, the power converter comprising:
a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device;
a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and
a control circuit to output a control signal for controlling the drive circuit to the drive circuit.

### Claim 8 (depends on 4)

A power converter including the semiconductor device according to claim 4, the power converter comprising:
a main converter circuit to convert input power and output converted power, the main converter circuit including the semiconductor device;
a drive circuit to output a driving signal for driving the semiconductor device to the semiconductor device; and
a control circuit to output a control signal for controlling the drive circuit to the drive circuit.