# US 10,872,957 B2 · Semiconductor device with needle-shaped field plate structures

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- Number: US 10,872,957 B2
- Document ID: US10872957B2
- Status: Granted
- Kind: B2
- Application number: 16/691,828
- Filed: 2019-11-22
- Published: 2020-04-23
- Granted: 2020-12-22
- Earliest claimed: 2016-02-25
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Ralf Siemieniec; Oliver Blank; Franz Hirler; Michael Hutzler; David Laforet; Cedric Ouvrard; Li Juin Yip
- Web page: https://patentgrep.com/patent/US10872957B2

## CPC

- H10D 64/112: {comprising multiple field plate segments}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a transistor cell region formed in the semiconductor substrate and comprising a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate; and
an inner termination region formed in the semiconductor substrate and devoid of transistor cells, the inner termination region surrounding the transistor cell region and comprising needle-shaped second field plate structures extending from the first surface into the semiconductor substrate,
wherein the first field plate structures and the second field plate structures have the same layout.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure forms a grid having meshes with gaps which surround the transistor sections, and wherein connection sections of the semiconductor substrate form bridges between neighboring ones of the transistor sections.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein center-to-center distances between neighboring second field plate structures, between neighboring first and second field plate structures, and between neighboring first field plate structures are equal.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure forms a grid having uninterrupted meshes which surround the transistor sections.

### Claim 5

A semiconductor device, comprising:
a semiconductor substrate;
a transistor cell region formed in the semiconductor substrate and comprising a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate; and
an inner termination region formed in the semiconductor substrate and devoid of transistor cells, the inner termination region surrounding the transistor cell region and comprising needle-shaped second field plate structures extending from the first surface into the semiconductor substrate,
wherein the first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein center points of the second field plate structures and center points of the first field plate structures are equally spaced such that the second field plate structures and the first field plate structures complement each other in a regular pattern.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the gate structure forms a grid having meshes with gaps which surround the transistor sections, and wherein connection sections of the semiconductor substrate form bridges between neighboring ones of the transistor sections.

### Claim 8 (depends on 5)

The semiconductor device of claim 5, wherein center-to-center distances between neighboring second field plate structures, between neighboring first and second field plate structures, and between neighboring first field plate structures are equal.

### Claim 9 (depends on 5)

The semiconductor device of claim 5, wherein an arrangement of center points of the second field plate structures is congruent to an arrangement of center points of a portion of the first field plate structures.

### Claim 10 (depends on 5)

The semiconductor device of claim 5, wherein the gate structure forms a grid having uninterrupted meshes which surround the transistor sections.

### Claim 11 (depends on 5)

The semiconductor device of claim 5, further comprising:
an auxiliary electrode and second contact structures electrically connecting, in the termination region, the auxiliary electrode with second field electrodes in the second field plate structures.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the auxiliary electrode is electrically connected with a first load electrode that is electrically connected with first field electrodes in the first field plate structures.

### Claim 13 (depends on 5)

The semiconductor device of claim 5, further comprising:
a transition region interposed between the transistor cell region and the inner termination region, the transition region forming a first pn junction with a drift structure of the transistor cell region, the first pn junction extending to the first surface of the semiconductor substrate.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the first pn junction extends horizontally between neighboring ones of the second field plate structures aligned in a same row, and wherein the second field plate structures in the same row have the same distance to the transistor cell region.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein the transition region comprises connection portions of the gate structure.

### Claim 16 (depends on 5)

The semiconductor device of claim 5, further comprising:
an outer termination region interposed between a lateral outer surface of the semiconductor substrate and an outermost one of the second field plate structures, the lateral outer surface extending from the first surface to a second surface of the semiconductor substrate.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein an outer section of the outer termination region is devoid of regions of a second conductivity type that are spaced from the second surface of the semiconductor substrate and that form pn junctions with a drift structure of the transistor cell region.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the outer termination region comprises a conductive structure electrically connected to the drift structure.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the conductive structure comprises a conductive fill of a trench structure extending from the first surface into the semiconductor substrate.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein the conductive structure comprises a heavily doped region directly adjoining the first surface.