# US 10,872,955 B2 · Semiconductor device and fabricating method thereof

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- Number: US 10,872,955 B2
- Document ID: US10872955B2
- Status: Granted
- Kind: B2
- Application number: 16/693,048
- Filed: 2019-11-22
- Published: 2020-03-26
- Granted: 2020-12-22
- Earliest claimed: 2017-11-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Chieh Lu; Meng-Hsuan Hsiao; Tung-Ying Lee; Ling-Yen Yeh; Chih-Sheng Chang; Carlos H. Diaz
- Web page: https://patentgrep.com/patent/US10872955B2

## CPC

- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/36: {the transistor being a FinFET}
- H10B 51/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B 51/40: characterised by the peripheral circuit region
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 62/113: {Isolations within a component, i.e. internal isolations}
- H10D 62/149: {Source or drain regions of field-effect devices}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/314: {having vertical doping variations (vertical IGFETs H10D30/63)}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/01356: {the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence)}
- H10D 64/01358: {the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material}
- H10D 64/689: {having ferroelectric layers}
- H10D 84/853: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 50/20: Dry etching; Plasma etching; Reactive-ion etching
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 95/70: Chemical treatments
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/80: characterised by the materials
- H10D 62/881: {being a two-dimensional material}
- H10D 62/883: {Transition metal dichalcogenides, e.g. MoSe2}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3402: {characterised by the chemical composition}
- H10P 14/3436: {being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/68: Organic materials, e.g. photoresists
- H10P 76/204: {of organic photoresist masks}
- H10P 95/062: {involving a dielectric removal step}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a fin structure extending along a first direction, a channel layer wrapping around a top surface and opposite sidewalls of the fin structure, a gate stack extending across the channel layer along a second direction perpendicular to the first direction, and a spacer on a top surface of the channel layer and a sidewall of the gate stack when viewed in a cross section taken along the first direction. The channel layer includes a two-dimensional material. The gate stack includes a ferroelectric layer.

## Claims

### Claim 1

A semiconductor device comprising:
a fin structure extending along a first direction;
a channel layer wrapping around a top surface and opposite sidewalls of the fin structure, wherein the channel layer includes a two-dimensional material;
a gate stack extending across the channel layer along a second direction perpendicular to the first direction, wherein the gate stack includes a ferroelectric layer; and
a spacer on a top surface of the channel layer and a sidewall of the gate stack when viewed in a cross section taken along the first direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the gate stack further includes a cap layer on a top surface of the ferroelectric layer and a gate layer on a top surface of the cap layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising a passivation layer sandwiched between the fin structure and the channel layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising a passivation layer sandwiched between the fin structure and the spacer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a source/drain metal layer on a sidewall of the spacer when viewed in the cross section take along the first direction.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a source/drain metal layer on a sidewall of the channel layer when viewed in a cross section taken along the second direction.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising a source/drain metal layer that has a top surface substantially coplanar with a top surface of the gate stack.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a source/drain metal layer on the fin structure;
a metal glue layer on a sidewall of the source/drain metal layer; and
a contact plug on a top surface of the metal glue layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising:
a source/drain metal layer; and
a passivation layer sandwiched between the fin structure and the source/drain metal layer.

### Claim 10

A semiconductor device comprising:
a fin structure;
a 2D-material passivation layer wrapping around three sides of the fin structure;
a 2D-material channel layer wrapping around three sides of the 2D-material passivation layer; and
a gate stack wrapping around three sides of the 2D-material channel layer, wherein the gate stack includes a ferroelectric layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising a spacer alongside the gate stack and a source/drain metal layer adjacent the spacer.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, further comprising a source/drain metal layer having a top surface substantially coplanar with a top surface of the gate stack.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, further comprising:
a source/drain metal layer on a top surface of the 2D-material passivation layer;
a metal glue layer on a sidewall of the source/drain metal layer; and
a contact plug on a top surface of the metal glue layer.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, further comprising:
a source/drain metal layer, wherein the 2D-material passivation layer is between the fin structure and the source/drain metal layer.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein the gate stack further includes a cap layer on a top surface of the ferroelectric layer and a gate layer on a top surface of the cap layer.

### Claim 16

A semiconductor device comprising:
a fin structure extending along a first direction;
a gate stack extending across the fin structure along a second direction different from the first direction; and
a 2D-material channel layer wrapping around three sides of the fin structure and being wrapped around by a ferroelectric layer of the gate stack when viewed in a cross section taken along the second direction.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising:
a boron nitride layer wrapped around by the 2D-material channel layer when viewed in the cross section taken along the second direction.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the gate stack further comprises a capping metal layer wrapping around the ferroelectric layer when viewed in the cross section taken along the second direction.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the gate stack further comprises a polysilicon layer wrapping around the capping metal layer when viewed in the cross section taken along the second direction.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, further comprising:
a source/drain metal layer wrapping around the three sides of the fin structure when viewed in another cross section taken along the second direction.