# US 10,872,954 B2 · Sidewall image transfer nanosheet

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- Number: US 10,872,954 B2
- Document ID: US10872954B2
- Status: Granted
- Kind: B2
- Application number: 16/853,161
- Filed: 2020-04-20
- Published: 2020-08-06
- Granted: 2020-12-22
- Earliest claimed: 2015-12-28
- Assignees: Tessera, Inc.
- Applicants: Tessera, Inc.
- Inventors: Effendi Leobandung; Tenko Yamashita
- Web page: https://patentgrep.com/patent/US10872954B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 14/3462: {Nanowires}
- H10P 50/642: {Chemical etching}
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming active regions of a semiconductor device comprising forming a nanosheet stack on a substrate, forming the nanosheet stack comprising forming a sacrificial nanosheet layer on the substrate, and forming a nanosheet layer on the sacrificial nanosheet layer, forming an etch stop layer on the nanosheet stack, forming a mandrel layer on the etch stop layer, removing portions of the mandrel layer to form a mandrel on the etch stop layer, forming sidewalls adjacent to sidewalls of the mandrel, depositing a fill layer on exposed portions of the etch stop layer, removing the sidewalls and removing exposed portions of the etch stop layer and the nanosheet stack to expose portions of the substrate.

## Claims

### Claim 1

A structure comprising:
a substrate;
a first set of semiconductor nanosheets vertically disposed on the substrate, the first set of semiconductor nanosheets comprising a first channel region;
a second set of semiconductor nanosheets vertically disposed on the substrate, the second set of semiconductor nanosheets comprising a second channel region;
a gate stack having an elongated axis in a first direction, disposed on the substrate and over and around both the first and second channel regions;
first source and drain regions disposed on opposite sides of the first channel region in a second direction orthogonal to the first direction;
second source and drain regions disposed on opposite sides of the second channel region in the second direction;
wherein the first and second channel regions are at the same level of their respective sets of semiconductor nanosheets and are separated by a distance of about 2 nanometers (nm) to about 10 nm in the first direction.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the first channel region has a width in the first direction of approximately 10-50 nm and the second channel region has a width in the first direction of approximately 10-50 nm.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the first and second sets of semiconductor nanosheets comprise epitaxially grown semiconductor material.

### Claim 4 (depends on 1)

The structure of claim 1, wherein the gate stack comprises:
a high-k dielectric; and
a work function layer disposed over and around the high-k dielectric.

### Claim 5 (depends on 4)

The structure of claim 4, wherein the high-k dielectric comprises a dopant.

### Claim 6 (depends on 5)

The structure of claim 5, wherein the dopant is lanthanum.

### Claim 7 (depends on 5)

The structure of claim 5, wherein the dopant is aluminum.

### Claim 8 (depends on 1)

The structure of claim 1, wherein the first and second source regions comprise a merged, epitaxially grown semiconductor material.

### Claim 9 (depends on 1)

The structure of claim 1, wherein the first and second drain regions comprise a merged, epitaxially grown semiconductor material.

### Claim 10

A structure comprising:
a substrate;
a first set of semiconductor nanosheets vertically disposed on the substrate, the first set of semiconductor nanosheets comprising a first channel region;
a second set of semiconductor nanosheets vertically disposed on the substrate, the second set of semiconductor nanosheets comprising a second channel region;
a gate stack having an elongated axis in a first direction, disposed on the substrate and over and around both the first and second channel regions;
first source and drain regions disposed on opposite sides of the first channel region in a second direction orthogonal to the first direction;
second source and drain regions disposed on opposite sides of the second channel region in the second direction;
wherein the first and second channel regions are at the same level of their respective sets of semiconductor nanosheets and are separated by a sublithographic distance.

### Claim 11 (depends on 10)

The structure of claim 10, wherein the sublithographic distance is about 2 nm to about 10 nm, and is formed by selectively removing a sidewall followed by an etch.

### Claim 12 (depends on 10)

The structure of claim 10, wherein the first channel region has a width in the first direction of approximately 10-50 nm and the second channel region has a width in the first direction of approximately 10-50 nm.

### Claim 13 (depends on 10)

The structure of claim 10, wherein the first and second sets of semiconductor nanosheets comprise epitaxially grown semiconductor material.

### Claim 14 (depends on 10)

The structure of claim 10, wherein the gate stack comprises:
a high-k dielectric; and
a work function layer disposed over and around the high-k dielectric.

### Claim 15 (depends on 14)

The structure of claim 14, wherein the high-k dielectric comprises a dopant.

### Claim 16 (depends on 15)

The structure of claim 15, wherein the dopant is lanthanum.

### Claim 17 (depends on 15)

The structure of claim 15, wherein the dopant is aluminum.

### Claim 18 (depends on 10)

The structure of claim 10, wherein the first and second source regions comprise a merged, epitaxially grown semiconductor material.

### Claim 19 (depends on 10)

The structure of claim 10, wherein the first and second drain regions comprise a merged, epitaxially grown semiconductor material.