# US 10,872,953 B2 · Nanosheet substrate isolated source/drain epitaxy by counter-doped bottom epitaxy

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- Number: US 10,872,953 B2
- Document ID: US10872953B2
- Status: Granted
- Kind: B2
- Application number: 15/872,610
- Filed: 2018-01-16
- Published: 2019-07-18
- Granted: 2020-12-22
- Earliest claimed: 2018-01-16
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Alexander Reznicek; Bahman Hekmatshoartabari
- Web page: https://patentgrep.com/patent/US10872953B2

## CPC

- H10D 62/114: {PN junction isolations}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/051: {of isolation region based on field-effect}
- H10W 10/30: Isolation regions comprising PN junctions
- H10W 10/50: Isolation regions based on field-effect
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming a counter doped semiconductor layer on a physically exposed and recessed surface of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The presence of the counter doped semiconductor layer isolates the source/drain regions from the semiconductor substrate and eliminates parasitic transistor formation.

## Claims

### Claim 1

A semiconductor structure comprising:
a plurality of stacked and suspended semiconductor channel material nanosheets located above a semiconductor substrate that is composed of a semiconductor material of a first conductivity type, wherein the semiconductor substrate includes a lower region having a first dopant concentration, a middle region having a second dopant concentration and an upper region having a third dopant concentration, wherein the second dopant concentration is less than the first and third dopant concentrations;
a functional gate structure surrounding a portion of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets;
a counter doped semiconductor layer composed of a semiconductor material of a second conductivity type that is different from the first conductivity type and located on a recessed surface of the semiconductor substrate; and
a source/drain (S/D) region on each side of the functional gate structure and physically contacting sidewalls of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets, wherein the source/drain (S/D) region is located directly on a surface of the counter doped semiconductor layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the counter doped semiconductor layer extends through the upper region of the semiconductor substrate and into a portion of the middle region of the semiconductor substrate.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, further comprising inner gate spacers contacting sidewalls of the functional gate structure and located on an outer portion of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein each source/drain (S/D) region has a faceted upper surface.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, further comprising an interlevel dielectric (ILD) material located above each S/D region.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the ILD material atop each S/D region has a topmost surface that is coplanar with a topmost surface of the functional gate structure.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the sidewalls of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets are vertically aligned to each other.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor substrate and each semiconductor channel material nanosheet is composed of a same semiconductor material.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein no parasitic transistor is present beneath the plurality of stacked and suspended semiconductor channel material nanosheets.

### Claim 10

A method of forming a semiconductor structure, the method comprising:
providing a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet located on a surface of a semiconductor substrate composed of a semiconductor material of a first conductivity type, wherein a sacrificial gate structure and a dielectric spacer material layer straddle over the nanosheet stack, and the semiconductor substrate has physically exposed recessed surfaces that lay adjacent the sacrificial gate structure and the dielectric spacer material layer, wherein the semiconductor substrate includes a lower region having a first dopant concentration, a middle region having a second dopant concentration and an upper region having a third dopant concentration, wherein the second dopant concentration is less than the first and third dopant concentrations;
recessing end portions of each of the sacrificial semiconductor material nanosheets to provide a gap between each of the semiconductor channel material nanosheets;
forming an additional dielectric spacer material layer on the dielectric spacer material layer and within each gap and on the recessed surfaces of the semiconductor substrate;
removing the additional dielectric spacer material layer from the recessed surfaces to re-expose the recessed surface;
forming a counter doped semiconductor layer composed of a semiconductor material of a second conductivity type that differs from the first conductivity type on the re-exposed recessed surfaces of the semiconductor substrate;
physically exposing sidewalls of each semiconductor channel material nanosheet; and
forming a source/drain (S/D) region by epitaxial growth of a semiconductor material on the physically exposed sidewalls of each semiconductor channel material nanosheet, wherein each S/D region is present on a surface of one of the counter doped semiconductor layers.

### Claim 11 (depends on 10)

The method of claim 10, further comprising forming an interlevel dielectric (ILD) material atop each S/D region.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
removing the sacrificial gate structure; and
removing each sacrificial semiconductor material nanosheet to suspend each semiconductor channel material nanosheet.

### Claim 13 (depends on 12)

The method of claim 12, further comprising forming a functional gate structure in regions occupied by the sacrificial gate structure and each sacrificial semiconductor material nanosheet, wherein the functional gate structure warps around each suspended semiconductor channel material nanosheet.

### Claim 14 (depends on 10)

The method of claim 10, further comprising recessing the recessed surfaces of the semiconductor substrate, wherein the recessing of the recessed surfaces of the semiconductor substrate is performed after removing the additional dielectric spacer material layer from the recessed surfaces and prior to the forming of the counter doped semiconductor layer.

### Claim 15 (depends on 10)

The method of claim 10, wherein the forming of the counter doped semiconductor layer comprises an epitaxial growth process.

### Claim 16 (depends on 10)

The method of claim 10, wherein the recessing end portions of each sacrificial semiconductor material nanosheet comprises a lateral etching process.

### Claim 17

A method of forming a semiconductor structure, the method comprising:
providing a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet located on a surface of a semiconductor substrate composed of a semiconductor material of a first conductivity type, wherein a sacrificial gate structure and a dielectric spacer material layer straddle over the nanosheet stack, and the semiconductor substrate has physically exposed recessed surfaces that lay adjacent the sacrificial gate structure and the dielectric spacer material layer, wherein each sacrificial semiconductor material nanosheet is composed of a first semiconductor material, and each semiconductor channel material nanosheet is composed of a second semiconductor material that differs from, and has a different etch rate than, the first semiconductor material;
recessing end portions of each of the sacrificial semiconductor material nanosheets to provide a gap between each of the semiconductor channel material nanosheets;
forming an additional dielectric spacer material layer on the dielectric spacer material layer and within each gap and on the recessed surfaces of the semiconductor substrate;
removing the additional dielectric spacer material layer from the recessed surfaces to re-expose the recessed surface;
forming a counter doped semiconductor layer composed of a semiconductor material of a second conductivity type that differs from the first conductivity type on the re-exposed recessed surfaces of the semiconductor substrate;
physically exposing sidewalls of each semiconductor channel material nanosheet; and
forming a source/drain (S/D) region by epitaxial growth of a semiconductor material on the physically exposed sidewalls of each semiconductor channel material nanosheet, wherein each S/D region is present on a surface of one of the counter doped semiconductor layers.

### Claim 18 (depends on 17)

The method of claim 17, wherein the semiconductor substrate includes a lower region having a first dopant concentration, a middle region having a second dopant concentration and an upper region having a third dopant concentration, wherein the second dopant concentration is less than the first and third dopant concentrations.

### Claim 19 (depends on 18)

The method of claim 18, wherein the counter doped semiconductor layer extends through the upper region of the semiconductor substrate and into a portion of the middle region of the semiconductor substrate.