# US 10,872,926 B2 · Vector-matrix multiplication accelerator implemented using folded resistive crossbars

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- Number: US 10,872,926 B2
- Document ID: US10872926B2
- Status: Granted
- Kind: B2
- Application number: 16/392,845
- Filed: 2019-04-24
- Published: 2020-10-29
- Granted: 2020-12-22
- Earliest claimed: 2019-04-24
- Applicants: Tetramem Inc.
- Inventors: Ning Ge
- Web page: https://patentgrep.com/patent/US10872926B2

## CPC

- G11C 11/54: using elements simulating biological cells, e.g. neuron
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- G11C 7/16: Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
- G11C 13/0023: {Address circuits or decoders}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/003: {Cell access}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- G06N 3/065: Analogue means
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

Technologies relating to folded crossbar array circuits and methods for reducing pitch match issues within folded crossbar array circuits and increasing the scalability of folded crossbar array circuits are disclosed. An example crossbar array circuit includes: a first folded column circuit folded as at least two portions; a first ADC; a first plurality of DACs; and a first plurality of access controls, wherein the first folded column circuit connected to the first ADC, the first plurality of DACs, and the first plurality of access controls. In some implementations, the three portions comprises a first column of crossbar devices, a second column of crossbar devices, and a third column of crossbar devices, and wherein the first column of crossbar devices, the second column of crossbar devices, and the third column of crossbar devices are configured to be controlled by the first plurality of access controls.

## Claims

### Claim 1

A crossbar array circuit comprising:
a first folded column circuit folded as at least two portions;
a first analog-to-digital converter (ADC);
a first plurality of digital-to-analog converters (DACs); and
a first plurality of access controls, wherein
the first folded column circuit connected to the first ADC, the first plurality of DACs, and the first plurality of access controls.

### Claim 2 (depends on 1)

The crossbar array circuit as claimed in claim 1, wherein a folding style of the first folded column circuit comprises an accordion fold.

### Claim 3 (depends on 1)

The crossbar array circuit as claimed in claim 1, wherein the two portions comprises a first column of crossbar devices, a second column of crossbar devices, and a third column of crossbar devices, and wherein the first column of crossbar devices, the second column of crossbar devices, and the third column of crossbar devices are configured to be controlled by the first plurality of access controls.

### Claim 4 (depends on 3)

The crossbar array circuit as claimed in claim 3, wherein the first column of crossbar devices comprises a first crossbar device, the second column of crossbar devices comprises a second crossbar device, and the third column of crossbar devices comprises a third crossbar device, and wherein the first crossbar device, the second crossbar device, or the third crossbar device comprises an access transistor configured to be controlled by the first plurality of access controls.

### Claim 5 (depends on 4)

The crossbar array circuit as claimed in claim 4, wherein the first crossbar device, the second crossbar device, or the third crossbar device comprises an RRAM device.

### Claim 6 (depends on 4)

The crossbar array circuit as claimed in claim 4, wherein a number of folds is determined in accordance with a ratio of a line width of the first column of crossbar devices to a width of the first ADC.

### Claim 7 (depends on 6)

The crossbar array circuit as claimed in claim 6, further comprises:
a plurality of folded column circuits comprising the first folded column circuit; and
a plurality of ADCs comprising the first ADC, wherein the plurality of folded column circuits connected to the plurality of ADCs, the first plurality of DACs, and the first plurality of access controls.

### Claim 8 (depends on 7)

The crossbar array circuit as claimed in claim 7, wherein a ratio of a number of total columns in the crossbar array circuit to a number of total ADCs in the crossbar array circuit is the number of folds.

### Claim 9 (depends on 1)

The crossbar array circuit as claimed in claim 1 further comprises a ramping circuit connected to the first plurality of DACs.

### Claim 10 (depends on 9)

The crossbar array circuit as claimed in claim 9, wherein the ramping circuit comprises a ramping signal generator and a clock.