# US 10,872,919 B2 · Solid-state imaging device and electronic apparatus

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- Number: US 10,872,919 B2
- Document ID: US10872919B2
- Status: Granted
- Kind: B2
- Application number: 16/069,448
- Filed: 2017-01-13
- Published: 2019-01-17
- Granted: 2020-12-22
- Earliest claimed: 2016-01-29
- Assignees: Sony Corporation
- Applicants: Sony Corporation
- Inventors: Masaaki Takizawa; Yasushi Tateshita; Takahiro Toyoshima; Takuya Toyofuku; Yorito Sakano; Motonobu Torii
- Web page: https://patentgrep.com/patent/US10872919B2

## CPC

- H10F 39/807: {Pixel isolation structures}
- H04N 25/441: by reading contiguous pixels from selected rows or columns of the array, e.g. interlaced scanning
- H04N 25/585: with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
- H04N 25/59: by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
- H04N 25/62: Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
- H04N 25/70: SSIS architectures; Circuits associated therewith
- H04N 25/702: SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout
- H04N 25/75: Circuitry for providing, modifying or processing image signals from the pixel array
- H04N 25/771: comprising storage means other than floating diffusion
- H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/12: Image sensors
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/182: {Colour image sensors}
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes}
- H10F 39/8023: {Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery}
- H10F 39/8027: {Geometry of the photosensitive area}
- H10F 39/8033: {Photosensitive area}
- H10F 39/80373: {characterised by the gate of the transistor}
- H10F 39/8057: {Optical shielding}
- H10F 39/8063: {Microlenses}
- H10F 39/813: {Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels}
- H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices
- H10W 10/01: {Manufacture or treatment}
- H04N 25/53: Control of the integration time
- H10F 39/8053: {Colour filters}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are a solid-state imaging device and an electronic apparatus that include a charge storage unit. The charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. The charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a half (one side) of a surface of the hole, and an insulating film and an upper electrode are formed so as to the hole.

## Claims

### Claim 1

A solid-state imaging device, comprising:
a pixel array including a plurality of unit pixels; and
a circuit configured to control an operation of the plurality of unit pixels,
wherein each of the plurality of unit pixels includes:
a photodiode configured to generate a charge;
a trench capacitor configured to store the charge generated by the photodiode; and
a reverse-side deep trench isolation (RDTI) joined to the trench capacitor,
wherein the RDTI is adjacent to the trench capacitor.

### Claim 2 (depends on 1)

The solid-state imaging device according to claim 1, wherein
the trench capacitor is between the photodiode of a first unit pixel of the plurality of unit pixels and the photodiode of a second unit pixel of the plurality of unit pixels, and
the first unit pixel is adjacent to the second unit pixel.

### Claim 3 (depends on 1)

The solid-state imaging device according to claim 1, wherein
each of the plurality of unit pixels further includes a plurality of photodiodes,
the trench capacitor is one of between the plurality of photodiodes or between a first photodiode of the plurality of photodiodes of a first unit pixel of the plurality of unit pixels and a second photodiode of the plurality of photodiodes of a second unit pixel of the plurality of unit pixels, and
the first unit pixel is adjacent to the second unit pixel.

### Claim 4 (depends on 1)

The solid-state imaging device according to claim 1, wherein the trench capacitor penetrates a substrate.

### Claim 5 (depends on 1)

The solid-state imaging device according to claim 1, wherein
a potential of one end of the trench capacitor is one of a ground potential, a power-supply potential, or a specific potential.

### Claim 6 (depends on 5)

The solid-state imaging device according to claim 5, wherein
the potential of the one end of the trench capacitor is set at a first potential at a storing time of the photodiode,
the potential of the one end of the trench capacitor is set at a second potential at a reading time of the photodiode, and
the first potential is different from the second potential.

### Claim 7 (depends on 1)

The solid-state imaging device according to claim 1, wherein the solid-state imaging device is of a backside-illuminated type.

### Claim 8

An electronic apparatus, comprising:
a solid-state imaging device including:
a pixel array including a plurality of unit pixels; and
a circuit configured to control an operation of the plurality of unit pixels, wherein
each of the plurality of unit pixels includes:
a photodiode configured to generate a charge;
a trench capacitor configured to store the charge generated by the photodiode; and
a reverse-side deep trench isolation (RDTI) joined to the trench capacitor,
wherein the RDTI is adjacent to the trench capacitor;
a signal processing circuit configured to process an output signal output from the solid-state imaging device; and
an optical system configured to provide incident light to the solid-state imaging device.