# US 10,872,909 B2 · Transistor display panel having an auxiliary layer overlapping portions of source and gate electrodes

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- Number: US 10,872,909 B2
- Document ID: US10872909B2
- Status: Granted
- Kind: B2
- Application number: 16/725,958
- Filed: 2019-12-23
- Published: 2020-04-30
- Granted: 2020-12-22
- Earliest claimed: 2017-10-19
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Byung Hwan Chu; Sho Yeon Kim; Wan-Soon Im; Yong Tae Cho
- Web page: https://patentgrep.com/patent/US10872909B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 86/431: {having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 30/6729: {characterised by the electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

## Claims

### Claim 1

A transistor display panel comprising:
a substrate;
a gate line disposed over the substrate and extending in a first direction;
a gate electrode extending from the gate line;
a gate insulating layer disposed over the gate line and the gate electrode;
a semiconductor layer disposed over the gate insulating layer;
at least one auxiliary layer disposed over the gate insulating layer and spaced apart from the semiconductor layer;
a data line disposed over the gate insulating layer and extending in a second direction crossing the first direction;
a source electrode disposed over the gate insulating layer and the semiconductor layer, and extending from the data line toward the gate electrode;
a drain electrode disposed over the gate insulating layer and the semiconductor layer, and spaced apart from the data line; and
a pixel electrode connected to the drain electrode,
wherein the at least one auxiliary layer overlaps a portion of the gate electrode and a portion of the source electrode in a plan view.

### Claim 2 (depends on 1)

The transistor display panel of claim 1, wherein the semiconductor layer and the auxiliary layer comprise amorphous silicon.

### Claim 3 (depends on 2)

The transistor display panel of claim 2, wherein:
the gate electrode has a first edge, a second edge, and a third edge facing the second edge;
a portion of the first edge overlaps the drain electrode in a plan view; and
a portion of the second edge overlaps the source electrode in a plan view.

### Claim 4 (depends on 3)

The transistor display panel of claim 3, wherein the auxiliary layer is disposed to face at least one of the first edge, the second edge, and the third edge of the gate electrode in a plan view.

### Claim 5 (depends on 4)

The transistor display panel of claim 4,
wherein:
the auxiliary layer comprises:
a first auxiliary layer overlapping the portion of the source electrode and the portion of the gate electrode in a plan view; and
a second auxiliary layer spaced apart from the first auxiliary layer; and
the second auxiliary layer overlaps a portion of the source electrode and a portion of the gate electrode in a plan view.

### Claim 6 (depends on 1)

The transistor display panel of claim 1, wherein the source electrode has a U-shape, and the drain electrode has a portion inserted in the U-shape of the source electrode.

### Claim 7 (depends on 1)

The transistor display panel of claim 1, wherein the drain electrode extends in the second direction.

### Claim 8 (depends on 1)

The transistor display panel of claim 1, wherein the at least one auxiliary layer has a stepped structure according to an edge of the portion of the gate electrode.