# US 10,872,903 B2 · Three dimensional memory and methods of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,903 B2 - Document ID: US10872903B2 - Status: Granted - Kind: B2 - Application number: 16/716,177 - Filed: 2019-12-16 - Published: 2020-04-16 - Granted: 2020-12-22 - Earliest claimed: 2010-06-28 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Sanh D. Tang; John K. Zahurak - Web page: https://patentgrep.com/patent/US10872903B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 13/0097: {Erasing, e.g. resetting, circuits or methods} - G11C 16/10: Programming or data input circuits - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - H10B 41/10: characterised by the top-view layout - H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 43/10: characterised by the top-view layout - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10B 63/34: {of the vertical channel field-effect transistor type} - H10B 63/845: {the switching components being connected to a common vertical conductor} - H10D 30/0411: {of FETs having floating gates} - H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors} - H10D 30/689: {Vertical floating-gate IGFETs} - H10D 30/693: {Vertical IGFETs having charge trapping gate insulators} - H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures} - H10D 88/00: Three-dimensional [3D] integrated devices - H10W 20/031: {of conductive parts of the interconnections} - H10W 20/43: Layouts of interconnections - G11C 2213/71: Three dimensional array - H10D 64/037: {comprising charge-trapping insulators} - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described. ## Claims ### Claim 1 An apparatus comprising: conductive pillars extending outward from a substrate; memory cell strings, each of the memory cell strings is formed over a respective conductive pillar of the conductive pillars; a first control gate formed in a first device level, the memory cell strings including a memory cell string, the memory cell string including a first memory cell having a memory element formed in a cavity of the first control gate; a second control gate formed in a second device level, the memory cell string including a second memory cell having a memory element formed in a cavity of the second control gate; and a conductive channel extending between the first memory cell and the second memory cell and electrically coupled to a conductive pillar of the conductive pillars. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising: a first conductive region located on a first side of the conductive pillar and separated from the conductive pillar by a first dielectric material; and a second conductive region located on a second side opposite from the first side of the conductive pillar and separated from the conductive pillar by a second dielectric material. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the first conductive region is coupled to the second conductive region. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein each of the first and second conductive regions comprises polysilicon. ### Claim 5 (depends on 2) The apparatus of claim 2, wherein each of the first and second conductive regions comprises metal. ### Claim 6 (depends on 1) The apparatus of claim 1, further comprising a data line coupled to the conductive channel, wherein the data line is located between the substrate and the first and second memory cells. ### Claim 7 (depends on 1) The apparatus of claim 1, further comprising a data line coupled to the conductive channel, wherein the first and second memory cells are located between the data line and the substrate. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the memory element comprises polysilicon. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the memory element comprises a dielectric material. ### Claim 10 An apparatus comprising: a first conductive pillar and a second conductive pillar extending outward from a substrate; a first data line coupled to the first and second conductive pillars, the first data line located between the first and second conductive pillars and the substrate; a third conductive pillar and a fourth conductive pillars extending outward from the substrate; a second data line coupled to the third and fourth conductive pillars, the second data line located between the third and fourth conductive pillars and the substrate; a first memory cell string formed over the first conductive pillar; a second memory cell string formed over the second conductive pillar; a third memory cell string formed over the third conductive pillar; a fourth memory cell string formed over the fourth conductive pillar; a first control gate formed in a first device level; a second control gate formed in a second device level, wherein, the first memory cell string includes a first memory cell having a memory element formed in a first cavity of the first control gate, and a second memory cell having a memory element formed in a first cavity of the second control gate; the second memory cell string includes a third memory cell having a memory element formed in a second cavity of the first control gate, and a fourth memory cell having a memory element formed in a second cavity of the second control gate; the third memory cell string includes a fifth memory cell having a memory element formed in a third cavity of the first control gate, and a sixth memory cell having a memory element formed in a third cavity of the second control gate; and the fourth memory cell string includes a seventh memory cell having a memory element formed in a fourth cavity of the first control gate, and an eighth memory cell having a memory element formed in a fourth cavity of the second control gate. ### Claim 11 (depends on 10) The apparatus of claim 10, further comprising: a first conductive channel coupled to the first conductive pillar and extending between the first and second memory cells; a second conductive channel coupled to the second conductive pillar and extending between the third and fourth memory cells; a third conductive channel coupled to the third conductive pillar and extending between the fifth and sixth memory cells; and a fourth conductive channel coupled to the fourth conductive pillar and extending between the seventh and eighth memory cells. ### Claim 12 (depends on 10) The apparatus of claim 10, further comprising a first conductive gate including a first segment and a second segment coupled to the first segment, wherein: the first segment is located on a first side of each of the first and third conductive pillars and separated from the first and third conductive pillars by a first dielectric material; and the second segment is located on a second side of each of the first and third conductive pillars and separated from the first and third conductive pillars by a second dielectric material. ### Claim 13 (depends on 12) The apparatus of claim 12, further comprising a second conductive gate including a third a segment and a fourth segment coupled to the third segment, wherein: the third segment is located on a first side of each of the second and fourth conductive pillars and separated from the second and fourth conductive pillars by a third dielectric material; and the fourth segment is located on a second side of each of the second and fourth conductive pillars and separated from the second and fourth conductive pillars by a fourth dielectric material. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein each of the first and second conductive gates comprises polysilicon. ### Claim 15 (depends on 13) The apparatus of claim 13, wherein each of the first and second conductive gates comprises metal. ### Claim 16 (depends on 10) The apparatus of claim 10, wherein the memory element of each of the first, second, third, and fourth memory cells comprises one of polysilicon and a dielectric material. ### Claim 17 An apparatus comprising: a first conductive pillar and a second conductive pillar extending outward from a substrate; a third conductive pillar and a fourth conductive pillars extending outward from the substrate; a region including a conductive material, the region coupled to the first, second, third, and fourth conductive pillars, the region located between substrate and the first, second, third, and fourth conductive pillars; a first memory cell string formed over the first conductive pillar; a second memory cell string formed over the second conductive pillar; a third memory cell string formed over the third conductive pillar; a fourth memory cell string formed over the fourth conductive pillar; a first data line coupled to the first and second memory cell strings, the first and second memory cell strings located between the first data line and the substrate; a second data line coupled to the third and fourth memory cell strings, the third and fourth memory cell strings located between the second data line and the substrate; a first control gate formed in a first device level; a second control gate formed in a second device level, wherein, the first memory cell string includes a first memory cell having a memory element formed in a first cavity of the first control gate, and a second memory cell having a memory element formed in a first cavity of the second control gate; the second memory cell string includes a third memory cell having a memory element formed in a second cavity of the first control gate, and a fourth memory cell having a memory element formed in a second cavity of the second control gate; the third memory cell string includes a fifth memory cell having a memory element formed in a third cavity of the first control gate, and a sixth memory cell having a memory element formed in a third cavity of the second control gate; and the fourth memory cell string includes a seventh memory cell having a memory element formed in a fourth cavity of the first control gate, and an eighth memory cell having a memory element formed in a fourth cavity of the second control gate. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the memory element of each of the first, second, third, and fourth memory cells comprises polysilicon. ### Claim 19 (depends on 17) The apparatus of claim 17, wherein the memory element of each of the first, second, third, and fourth memory cells comprises a silicon nitride. ### Claim 20 (depends on 17) The apparatus of claim 17, further comprising: a first conductive channel coupled to the first conductive pillar and extending between the first and second memory cells; a second conductive channel coupled to the second conductive pillar and extending between the third and fourth memory cells; a third conductive channel coupled to the third conductive pillar and extending between the fifth and sixth memory cells; and a fourth conductive channel coupled to the fourth conductive pillar and extending between the seventh and eighth memory cells.