# US 10,872,897 B2 · Cutting metal gates in fin field effect transistors

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,872,897 B2
- Document ID: US10872897B2
- Status: Granted
- Kind: B2
- Application number: 16/876,525
- Filed: 2020-05-18
- Published: 2020-09-03
- Granted: 2020-12-22
- Earliest claimed: 2017-11-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Li-Wei Yin; Shu-Yuan Ku; Chun-Fai Cheng
- Web page: https://patentgrep.com/patent/US10872897B2

## CPC

- H10B 10/18: {Peripheral circuit regions}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0153: {using gate cut processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 64/01: Manufacture or treatment
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/834: {comprising FinFETs}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure includes a first metal gate disposed over a first device region of a semiconductor substrate, where the first metal gate includes a first work function metal layer, a second metal gate disposed over a second device region of the semiconductor substrate, where the second metal gate includes a second work function metal layer, a first gate cut feature separating the first metal gate, where sidewalls of the first gate cut feature are defined by the first work function metal layer and a bulk conductive layer, and a second gate cut feature separating the second metal gate, where sidewalls of the second gate cut feature are defined by the second work function metal layer but not by the bulk conductive layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a semiconductor substrate including a logic device region and a memory device region adjacent to the logic device region;
semiconductor fins protruding from the semiconductor substrate, wherein the semiconductor fins are oriented lengthwise in a first direction;
a first metal gate disposed over the semiconductor fins in the logic device region, wherein the first metal gate includes a first work function metal layer;
a second metal gate disposed over the semiconductor fins in the memory device region, wherein the first metal gate and the second metal gate are oriented lengthwise in a second direction generally perpendicular to the first direction, and wherein the second metal gate includes a second work function metal layer;
a first gate cut feature separating the first metal gate, wherein sidewalls of the first gate cut feature are defined by the first work function metal layer and a bulk conductive layer; and
a second gate cut feature separating the second metal gate, wherein sidewalls of the second gate cut feature are defined by the second work function metal layer but not by the bulk conductive layer, and wherein a bottom surface of the first gate cut feature is below a bottom surface of the second gate cut feature.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising isolation structures disposed over the semiconductor substrate, wherein the first and the second gate cut features extend to below a top surface of the isolation structures.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein each of the first and the second metal gates includes more than one work function metal layer.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein a composition of the first work function metal layer is the same as a composition of second work function metal layer.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the first metal gate is configured to have a longer gate length than the second metal gate.

### Claim 6

A semiconductor structure, comprising:
a semiconductor substrate including a first region and a second region adjacent to the first region, wherein the first region is a logic device region and the second region is a memory device region;
semiconductor fins protruding from the semiconductor substrate, wherein the semiconductor fins are oriented lengthwise in a first direction;
a first metal gate disposed over the semiconductor fins in the first region of the semiconductor substrate, wherein the first metal gate is defined by a first gate length;
a first isolation feature disposed on a sidewall of the first metal gate, wherein the first isolation feature contacts a work function metal layer and a bulk conductive layer of the first metal gate;
a second metal gate disposed over the semiconductor fins in the second region of the semiconductor substrate, wherein the first metal gate and the second metal gate are oriented lengthwise in a second direction generally perpendicular to the first direction, wherein the second metal gate is defined by a second gate length that is less than the first gate length, and wherein the second metal gate includes the work function metal layer but is free of any bulk conductive layer; and
a second isolation feature disposed on a sidewall of the second metal gate, wherein the second isolation feature contacts the work function metal layer of the second metal gate and wherein a bottom surface of the first isolation feature extends to below a bottom surface of the second isolation feature.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the work function metal layer is a first work function metal layer, the semiconductor structure further comprising a second work function metal layer over the first work function metal layer in each of the first and the second metal gates, wherein the first and the second work function metal layers are of the same conductivity type.

### Claim 8 (depends on 6)

The semiconductor structure of claim 6, wherein the work function metal layer is a first work function metal layer, the semiconductor structure further comprising a second work function metal layer over the first work function metal layer in each of the first and the second metal gates, wherein the first and the second work function metal layers are of different conductivity types.

### Claim 9 (depends on 6)

The semiconductor structure of claim 6, wherein the bulk conductive layer includes tungsten.

### Claim 10 (depends on 6)

The semiconductor structure of claim 6, wherein the memory device region includes a static random-access memory (SRAM) device.

### Claim 11

A semiconductor structure, comprising:
a semiconductor substrate including a first region and a second region adjacent to the first region;
semiconductor fins protruding from the semiconductor substrate in the first region and the second region, wherein the semiconductor fins are oriented lengthwise along a first direction;
a first metal gate stack disposed over the semiconductor fins in the first region and oriented lengthwise along a second direction generally perpendicular to the first direction;
a first gate cut feature separating the first metal gate stack, wherein sidewalls of the first gate cut feature are defined by a first work function metal layer, a second work function metal layer, and a bulk conductive layer, and wherein the first gate cut feature has a first length along the second direction;
a second metal gate stack disposed over the semiconductor fins in the second region and oriented lengthwise along the second direction; and
a second gate cut feature separating the second metal gate stack, wherein sidewalls of the second gate cut feature are defined by the first work function metal layer and the second work function metal layer but are free of contact with the bulk conductive layer, and wherein the second gate cut feature has a second length along the second direction, the second length being less than the first length.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, further comprising isolation structures disposed over the semiconductor substrate and separating bottom portions of the semiconductor fins, wherein the first and the second gate cut features extend to below a top surface of the isolation structures.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the first gate cut feature extends to below a bottom surface of the second gate cut feature.

### Claim 14 (depends on 11)

The semiconductor structure of claim 11, wherein the first and the second work function metal layers have the same conductivity type.

### Claim 15 (depends on 11)

The semiconductor structure of claim 11, wherein the first and the second work function metal layers have different conductivity types.

### Claim 16 (depends on 11)

The semiconductor structure of claim 11, wherein the bulk conductive layer includes tungsten.