# US 10,872,895 B2 · Method of manufacturing capacitor structure

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- Number: US 10,872,895 B2
- Document ID: US10872895B2
- Status: Granted
- Kind: B2
- Application number: 15/623,035
- Filed: 2017-06-14
- Published: 2017-10-05
- Granted: 2020-12-22
- Earliest claimed: 2015-02-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Tsung-Hsueh Yang; Chung-Chiang Min; Chang-Ming Wu; Shih-Chang Liu
- Web page: https://patentgrep.com/patent/US10872895B2

## CPC

- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10B 12/033: {the capacitor extending over the transistor}
- H10D 1/716: {having vertical extensions}
- H10W 20/076: {in via holes or trenches}
- H10B 12/02: {for one transistor one-capacitor [1T-1C] memory cells}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/312: {with a bit line higher than the capacitor}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device includes forming a source/drain region in a substrate. An interlevel dielectric layer is formed on the substrate. A conducting plug is formed in the interlevel dielectric layer. The conducting plug is electrically coupled to the source/drain region. A crown oxide is formed on the interlevel dielectric layer. A deep trench is formed in the crown oxide to expose a top wall and a sidewall of the conducting plug. A spacer is formed on the sidewall of the conducting plug. A metal-insulator-metal film is formed in the deep trench.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a source/drain region in a substrate;
forming a first interlevel dielectric layer on the substrate;
forming a conducting plug in the first interlevel dielectric layer such that the conducting plug is electrically coupled to the source/drain region;
forming a crown oxide on the first interlevel dielectric layer;
forming a deep trench in the crown oxide to expose a top wall and a sidewall of the conducting plug;
forming a spacer that is in contact with the sidewall of the conducting plug; and
forming a metal-insulator-metal film in the deep trench and on the spacer that is in contact with the sidewall of the conducting plug.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
lining the spacer on a sidewall and a bottom wall of the deep trench; and
removing the spacer on the bottom wall of the deep trench to expose the first interlevel dielectric layer.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
lining the spacer on a sidewall and a bottom wall of the deep trench; and
thinning the spacer on the sidewall of the deep trench.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
depositing the metal-insulator-metal film on the spacer, the first interlevel dielectric layer, and the conducting plug.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming a second interlevel dielectric layer on the metal-insulator-metal film and the crown oxide; and
forming a conductive layer on the second interlevel dielectric layer.

### Claim 6

A method of manufacturing a semiconductor device, the method comprising:
forming a first source/drain region in a substrate;
forming a first interlevel dielectric layer on the substrate;
forming a first conducting plug in the first interlevel dielectric layer such that the first conducting plug is electrically coupled to the first source/drain region;
forming a crown oxide on the first interlevel dielectric layer;
forming a deep trench in the crown oxide to expose the first conducting plug such that the first conducting plug protrudes from the first interlevel dielectric layer;
forming a spacer in the deep trench such that the spacer is thicker at a bottom sidewall of the deep trench than at a top sidewall of the deep trench; and
forming a metal-insulator-metal film in the deep trench and in contact with the top sidewall of the deep trench, wherein a bottommost portion of the metal-insulator-metal film is higher than a bottommost portion of the spacer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
removing the spacer on a bottom wall of the deep trench to expose the first conducting plug and the first interlevel dielectric layer.

### Claim 8 (depends on 6)

The method of claim 6, further comprising:
thinning the spacer on the top sidewall of the deep trench.

### Claim 9 (depends on 6)

The method of claim 6, further comprising:
depositing the metal-insulator-metal film on the spacer, the first interlevel dielectric layer, and the first conducting plug.

### Claim 10 (depends on 6)

The method of claim 6, further comprising:
forming a second conducting plug on a second source/drain region in the first interlevel dielectric layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a second interlevel dielectric layer on the metal-insulator-metal film and the crown oxide.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
forming a third conducting plug in the crown oxide and the second interlevel dielectric layer, the third conducting plug being electrically coupled to the second conducting plug.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
forming a conductive layer on the second interlevel dielectric layer, the conductive layer being electrically coupled to the third conducting plug.

### Claim 14 (depends on 6)

The method of claim 6, further comprising:
forming an etch stop layer between the crown oxide and the first interlevel dielectric layer.

### Claim 15 (depends on 6)

The method according to claim 6, wherein forming the spacer in the deep trench comprises:
forming a spacer layer in the deep trench after forming the deep trench of the crown oxide; and
selectively etching the spacer layer to form the spacer.

### Claim 16

A method of manufacturing a semiconductor device, the method comprising:
forming an etch stop layer over a first interlevel dielectric layer;
forming a crown oxide on the etch stop layer;
forming a deep trench in the crown oxide;
forming a spacer on a bottom sidewall and a top sidewall of the deep trench;
selectively etching the spacer to expose the top sidewall of the deep trench;
forming a metal-insulator-metal film in the deep trench; and
forming a second interlevel dielectric layer inside the deep trench, wherein forming the deep trench is performed such that a portion of a top surface of the first interlevel dielectric layer is exposed by the deep trench and such that the exposed portion of the top surface of the first interlevel dielectric layer is convex.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising:
removing the spacer on a bottom wall of the deep trench.

### Claim 18 (depends on 16)

The method according to claim 16, further comprising:
depositing the metal-insulator-metal film on the spacer on the bottom sidewall and a bottom wall of the deep trench.

### Claim 19 (depends on 16)

The method according to claim 16, wherein a bottommost portion of the second interlevel dielectric layer is higher than a bottommost portion of the spacer.

### Claim 20 (depends on 16)

The method according to claim 16, further comprising:
prior to forming the etch stop layer, forming a conducting plug in the first interlevel dielectric layer, wherein forming the second interlevel dielectric layer is performed such that a bottom surface of the second interlevel dielectric layer is higher than a top surface of the conducting plug.