# US 10,872,894 B2 · Memory circuitry having a pair of immediately-adjacent memory arrays having space laterally-there-between that has a conductive interconnect in the space > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,894 B2 - Document ID: US10872894B2 - Status: Granted - Kind: B2 - Application number: 16/044,887 - Filed: 2018-07-25 - Published: 2019-02-28 - Granted: 2020-12-22 - Earliest claimed: 2017-08-29 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Werner Juengling - Web page: https://patentgrep.com/patent/US10872894B2 ## CPC - H10B 12/00: Dynamic random access memory [DRAM] devices - G11C 11/408: Address circuits - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - H10D 1/716: {having vertical extensions} - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract In some embodiments, memory circuitry comprises a pair of immediately-adjacent memory arrays having space laterally there-between. The memory arrays individually comprise memory cells individually having upper and lower elevationally-extending transistors and a capacitor elevationally there-between. The memory arrays comprise individual rows that (a) have an upper access line above and directly electrically coupled to a lower access line, and (b) are directly electrically coupled to one another across the space. The lower access line in one of the rows extends across the space from one of the memory arrays to the other of the memory arrays. Another of the rows comprises a conductive interconnect extending across a portion of the space. The conductive interconnect includes a horizontally-extending portion within the space that is laterally offset from the another row. Other aspects and implementations are disclosed. ## Claims ### Claim 1 Memory circuitry comprising: a pair of immediately-adjacent memory arrays having space laterally there-between, the memory arrays individually comprising memory cells individually having upper and lower elevationally-extending transistors and a capacitor elevationally there-between; the memory arrays comprising individual rows that (a) have an upper access line above and directly electrically coupled to a lower access line, and (b) are directly electrically coupled to one another across the space; the lower access line in one of the rows extending across the space from one of the memory arrays to the other of the memory arrays; and another of the rows comprising a conductive interconnect extending across a portion of the space, the conductive interconnect including a horizontally-extending portion within the space that is laterally offset from the another row. ### Claim 2 (depends on 1) The memory circuitry of claim 1 wherein the upper access lines are directly above the lower access lines at least within the one and the other of the memory arrays. ### Claim 3 (depends on 1) The memory circuitry of claim 1 wherein the upper and lower elevationally-extending transistors are vertical or within 10° of vertical. ### Claim 4 (depends on 3) The memory circuitry of claim 3 wherein the upper and lower elevationally-extending transistors in the individual memory cells share a common straight-line axis along which current flows in operation through a channel of the respective upper and lower elevationally-extending transistors. ### Claim 5 (depends on 1) The memory circuitry of claim 1 wherein the upper access line in the one row does not extend across the space from the one memory array to the other memory array. ### Claim 6 (depends on 1) The memory circuitry of claim 1 wherein the horizontally-extending portion of the conductive interconnect and a horizontally-extending portion of the upper access line are in a common horizontal plane. ### Claim 7 (depends on 1) The memory circuitry of claim 1 wherein the horizontally-extending portion of the conductive interconnect is within the one row. ### Claim 8 (depends on 7) The memory circuitry of claim 7 wherein the horizontally-extending portion of the conductive interconnect is directly above the lower access line in the one row. ### Claim 9 (depends on 1) The memory circuitry of claim 1 wherein the upper and lower access lines in the individual rows are directly electrically coupled to one another with conductive material that is above the upper access lines. ### Claim 10 (depends on 9) The memory circuitry of claim 9 wherein the conductive material is directly above the upper access line in the space. ### Claim 11 (depends on 10) The memory circuitry of claim 10 wherein the conductive material is directly above the lower access line in the space. ### Claim 12 (depends on 1) The memory circuitry of claim 1 wherein the upper and lower access lines in the individual rows are directly electrically coupled to one another with a first conductive via that contacts an uppermost surface of the upper access line and with a second conductive via that contacts an uppermost surface of the lower access line. ### Claim 13 (depends on 12) The memory circuitry of claim 12 wherein the upper and lower access lines in the individual rows are directly electrically coupled to one another with conductive material that is above the upper access lines and directly against uppermost surfaces of each of the first and second conductive vias. ### Claim 14 (depends on 1) The memory circuitry of claim 1 wherein the horizontally-extending portion of the conductive interconnect is horizontally elongated. ### Claim 15 (depends on 14) The memory circuitry of claim 14 the horizontally-elongated portion of the conductive interconnect is totally laterally offset from the another row. ### Claim 16 (depends on 1) The memory circuitry of claim 1 wherein the memory cells individually are two transistor-one capacitor (2T-1C) memory cells. ### Claim 17 (depends on 1) The memory circuitry of claim 1 comprising multiple conductive vias extending from the upper digit line level to the lower digit line level within the space laterally of the horizontally-extending portion of the conductive interconnect. ### Claim 18 Memory circuitry comprising: a pair of immediately-adjacent memory arrays having space laterally there-between, the memory arrays individually comprising memory cells individually having upper and lower elevationally-extending transistors and a capacitor elevationally there-between; the memory arrays comprising individual rows that (a) have an upper access line above and directly electrically coupled to a lower access line, and (b) are directly electrically coupled to one another across the space; the lower access line in one of the rows extending across the space from one of the memory arrays to the other of the memory arrays; and another of the rows comprising a conductive interconnect that includes a horizontally-elongated portion extending across a portion of the space and that is longitudinally-aligned in and with the one row. ### Claim 19 Memory circuitry comprising two transistor-one capacitor (2T-1C) memory cells, comprising: a pair of immediately-adjacent 2T-1C memory arrays having space laterally there-between, the 2T-1C memory arrays individually comprising 2T-1C memory cells individually comprising upper and lower elevationally-extending transistors having a capacitor elevationally there-between; the 2T-1C memory arrays comprising columns of first comparative digit lines at an upper digit line level above and electrically coupled to columns of the upper elevationally-extending transistors, the 2T-1C memory arrays comprising columns of second comparative digit lines at a lower digit line level below and electrically coupled to columns of the lower elevationally-extending transistors; the 2T-1C memory arrays sharing first alternating rows and second alternating rows, the second alternating rows individually being between immediately-adjacent of the first alternating rows, individual of the first and second alternating rows having an upper access line in an upper access line level above a lower access line in a lower access line level, the upper access line and the lower access line in the individual first alternating rows and in the individual second alternating rows being directly electrically coupled together, the upper access line and the lower access line in the individual first alternating rows being directly electrically coupled together by a conductor interconnect that includes a horizontally-extending portion within the upper digit line level that is directly above both of the upper access line and the lower access line in that individual first alternating row, the individual first alternating rows in the 2T-1C memory arrays being directly electrically coupled to one another across the space, the individual second alternating rows in the 2T-1C memory arrays not being directly electrically coupled to one another across the space; the lower access line in alternating ones of the first alternating rows extending across the space from one of the 2T-1C memory arrays to the other of the 2T-1C memory arrays, the upper access line in alternating others of the first alternating rows not extending across the space from one of the 2T-1C memory arrays to the other of the 2T-1C memory arrays, the alternating other first alternating rows individually being between immediately-adjacent of the alternating ones of the first alternating rows; and individual of the alternating other first alternating rows in the one and the other 2T-1C memory arrays being directly electrically coupled to one another across the space by a conductive interconnect that includes one horizontally-elongated portion in the space in the upper digit line level and another horizontally-elongated portion in the space in the upper access line level, the another horizontally-elongated portion in the space being directly above the lower access line in an immediately-adjacent one of the alternating ones of the first alternating rows. ### Claim 20 (depends on 19) The memory circuitry of claim 19 comprising multiple conductive vias extending from the upper digit line level to the lower digit line level within the space laterally between two immediately-adjacent of alternating ones of the first alternating rows.