# US 10,872,893 B2 · Dual nitride stressor for semiconductor device and method of manufacturing

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- Number: US 10,872,893 B2
- Document ID: US10872893B2
- Status: Granted
- Kind: B2
- Application number: 16/665,823
- Filed: 2019-10-28
- Published: 2020-04-23
- Granted: 2020-12-22
- Earliest claimed: 2015-05-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Lin Yang; Chia-Cheng Ho; Chih Chieh Yeh; Cheng-Yi Peng; Tsung-Lin Lee
- Web page: https://patentgrep.com/patent/US10872893B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 62/82: Heterojunctions
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
forming a first fin structure and a second fin structure over a substrate;
forming a first gate structure over a first portion of the first fin structure and forming a second gate structure over a first portion of the second fin structure;
forming a compressive film over a second portion of the first fin structure;
exposing the compressive film to ultraviolet radiation;
forming first source/drain regions at the second portion of the first fin structure;
forming a tensile film over a second portion of the second fin structure; and
forming second source/drain regions at the second portion of the second fin structure,
wherein the first source/drain regions extend along and in contact with a side surface of the compressive film and extend vertically over a top of the compressive film.

### Claim 2 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the first source/drain regions at the second portion of the first fin structure comprise SiP.

### Claim 3 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the second source/drain regions at the second portion of the second fin structure comprise SiGe.

### Claim 4 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, further comprising:
forming the compressive film over the second portion of the second fin structure;
after exposing the compressive film to ultraviolet radiation, substantially removing the compressive film over the second portion of the first fin structure so that a residual portion of the compressive film remains before forming first source/drain regions at the second portion of the first fin structure;
removing the compressive film over the second portion of the second fin structure;
forming a dummy layer over the first fin structure;
forming the tensile film over the first fin structure and the dummy layer;
substantially removing the tensile film over the second portion of the second fin structure so that a residual portion of the tensile film remains before forming second source/drain regions at the second portion of the second structure; and
removing the tensile film and the dummy layer over the second portion of the first fin structure.

### Claim 5 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein an NMOS FET is formed at the first fin structure, and a PMOS FET is formed at the second fin structure.

### Claim 6 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1, wherein the compressive film is formed over a shallow trench isolation region.

### Claim 7

A semiconductor device comprising:
a first fin structure and a second fin structure;
a first gate structure disposed over a first portion of the fin structure and a second gate structure disposed over a first portion of the second fin structure;
a compressive film disposed over a second portion of the first fin structure and a tensile film disposed over a second portion of the second fin structure; and
source/drain regions formed at the second portion of the first fin structure and second portion of the second fin structure,
wherein the source/drain regions extend along and in contact with a side surface of the compressive film and extend vertically over a top of the compressive film.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the source/drain regions at the second portion of the first fin structure comprise SiP and the source/drain regions at the second portion of the second fin structure comprise SiGe.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7, wherein the compressive film and the tensile film comprise a nitride or an oxide.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the nitride or oxide is selected from the group of silicon nitride, carbon-doped silicon nitride, carbon-doped silicon oxide, silicon oxynitride, boron nitride, and boron carbon nitride.

### Claim 11 (depends on 7)

The semiconductor device according to claim 7, wherein an NMOS FET is formed at the first fin structure and a PMOS FET is formed at the second fin structure.

### Claim 12 (depends on 7)

The semiconductor device according to claim 7, further comprising a shallow trench isolation region disposed between the first fin structure and the second fin structure.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein the compressive film is disposed over the shallow trench isolation region.

### Claim 14

A semiconductor device comprising:
a first fin structure and a second fin structure;
a shallow trench isolation region disposed between the first fin structure and the second fin structure;
a first gate structure disposed over a first portion of the fin structure and a second gate structure disposed over a first portion of the second fin structure;
a compressive nitride film residue disposed over a second portion of the first fin structure and a tensile nitride film residue disposed over a second portion of the second fin structure; and
source/drain regions formed at the second portion of the first fin structure and second portion of the second fin structure,
wherein the source/drain regions extend laterally and vertically over the compressive film residue and the tensile nitride film residue, and
the compressive nitride film residue and the tensile nitride film residue are disposed over the shallow trench isolation region.

### Claim 15 (depends on 14)

The semiconductor device according to claim 14, wherein the source/drain regions are in direct contact with the compressive film residue.

### Claim 16 (depends on 14)

The semiconductor device according to claim 14, wherein the source/drain regions at the second portion of the first fin structure comprise SiP.

### Claim 17 (depends on 14)

The semiconductor device according to claim 14, wherein the source/drain regions at the second portion of the second fin structure comprise SiGe.

### Claim 18 (depends on 14)

The semiconductor device according to claim 14, wherein the compressive nitride film residue comprises silicon nitride, carbon-doped silicon nitride, silicon oxynitride, boron nitride, or boron carbon nitride.

### Claim 19 (depends on 14)

The semiconductor device according to claim 14, wherein an NMOS FET is formed at the first fin structure and a PMOS FET is formed at the second fin structure.

### Claim 20 (depends on 14)

The semiconductor device according to claim 14, wherein the compressive nitride film residue has a compressive stress of about −1 to about −2 GPa.