# US 10,872,892 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 10,872,892 B2
- Document ID: US10872892B2
- Status: Granted
- Kind: B2
- Application number: 16/443,416
- Filed: 2019-06-17
- Published: 2020-01-02
- Granted: 2020-12-22
- Earliest claimed: 2018-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Lung Chen; Long-Jie Hong; Kang-Min Kuo
- Web page: https://patentgrep.com/patent/US10872892B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/80: characterised by the materials
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a semiconductor device includes forming a first transistor structure and a second transistor structure on a substrate, wherein source/drain structures of the first transistor structure and the second transistor structure are merged. The first and second transistor structures are separated by etching the source/drain structures.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a first transistor structure and a second transistor structure on a substrate, wherein source/drain structures of the first transistor structure and the second transistor structure are merged;
forming a silicide layer over the merged source/drain structures;
forming an interlayer dielectric layer over the merged source/drain structures;
forming a gap in the interlayer dielectric layer in a region between the first and the second transistors; and
separating the first and second transistor structures by etching the merged source/drain structures.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the silicide layer is formed before forming the interlayer dielectric layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the silicide layer is formed after the gap is formed.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the gap exposes a portion of the source/drain structures, and the portion of source/drain structures that is exposed is etched during the etching the source/drain structures.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising forming an etch stop layer over the silicide layer.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising forming a photoresist layer over the interlayer dielectric layer.

### Claim 7

A method of manufacturing a semiconductor device including a plurality of fin field effect transistors (FinFETs), the method comprising:
forming a first fin structure and a second fin structure over a substrate, the first and second fin structures extending in a first direction in plan view,
forming an isolation insulating layer over the substrate so that lower portions of the first and second fin structures are embedded in the isolation insulating layer and upper portions of the first and second fin structures are exposed from the isolation insulating layer;
forming a gate structure over parts of the first and second fin structures, the gate structure including a gate pattern, a dielectric layer disposed between the gate pattern and the first and second fin structures, and a cap insulating layer disposed over the gate pattern, the gate structure extending in a second direction crossing the first direction in plan view;
recessing upper portions of the first and second fin structures,
forming an epitaxial source/drain structure over the recessed first fin structure and the recessed second fin structure,
wherein the epitaxial source/drain structure is a merged structure such that a void is formed between the merged source/drain structure and the isolation insulating layer; and
etching a portion of the merged epitaxial structure between the first and second fin structures to form a first epitaxial source/drain structure and a second epitaxial source/drain structure.

### Claim 8 (depends on 7)

The method according to claim 7, further comprising forming a fin sidewall on sidewalls of the first and second fin structures protruding from the isolation insulating layer and not covered by the gate structure, and on an upper surface of the isolation insulating layer after forming the gate structure,
wherein in the recessing upper portions of the first and second fin structures, a portion of the fin sidewall disposed on the side surfaces of the fin structures is removed and a portion of the fin sidewall disposed on lower side surfaces of the fin structures remains.

### Claim 9 (depends on 7)

The method according to claim 7, wherein in the recessing upper portions of the first and second fin structures, the first and second fin structures are recessed down below the upper surface of the isolation insulating layer.

### Claim 10 (depends on 7)

The method according to claim 7, further comprising, after the first and second epitaxial source/drain structures are formed:
forming a silicide layer on the merged first and second epitaxial source/drain structures;
forming an interlayer dielectric layer; and
forming a gap in the interlayer dielectric layer.

### Claim 11 (depends on 10)

The method according to claim 10, wherein the silicide layer is formed before forming the interlayer dielectric layer.

### Claim 12 (depends on 10)

The method according to claim 10, wherein the silicide layer is formed after the opening is formed.

### Claim 13 (depends on 10)

The method according to claim 10, further comprising forming an etch stop layer over the silicide layer.

### Claim 14 (depends on 7)

The method according to claim 7, further comprising, after the first and second epitaxial source/drain structures are formed:
removing the cap insulating layer, the gate pattern and the dielectric layer so as to make a gate space;
forming a gate dielectric layer in the gate space; and
forming a gate electrode on the gate dielectric layer in the gate space.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the gate dielectric layer is formed of a high-k material.

### Claim 16 (depends on 7)

The method according to claim 7, wherein the first and second source/drain structures comprise a first region comprising SiP having a first P concentration and a second region over the first region having a second P concentration, where the second P concentration is less than the first P concentration.

### Claim 17

A semiconductor device comprising a plurality of transistors disposed over a common substrate, comprising:
a first transistor comprising a plurality of first fin structures and a second transistor comprising a plurality of second fin structures;
a first merged source/drain structure disposed over the first plurality of fin structures; and
a second merged source drain structure disposed over the second plurality of fin structures,
wherein a pair of adjacent first fin structures are spaced apart by a distance Si and a pair of adjacent second fin structures are spaced apart by the distance S1,
wherein one of the first fin structures is spaced apart from one of the second fin structures adjacent to the one of the first fin structures by a distance S2,
wherein the first merged source/drain structure is spaced apart from the second merged source/drain structure by a distance S3, and
a ratio of S2/S3 ranges from 1.25/1 to 25/1, and
wherein the first and second merged source/drain structures each comprise a first region comprising SiP having a first P concentration and a second region over the first region having a second P concentration, where the second P concentration is less than the first P concentration.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a ratio S2/S1 ranges from 1.5/1 to 7.5/1.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein S3 ranges from 2 nm to 20 nm.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein S2 ranges from 25 nm to 75 nm.