# US 10,872,890 B2 · Semiconductor device

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- Number: US 10,872,890 B2
- Document ID: US10872890B2
- Status: Granted
- Kind: B2
- Application number: 15/894,825
- Filed: 2018-02-12
- Published: 2018-06-21
- Granted: 2020-12-22
- Earliest claimed: 2015-12-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Che-Cheng Chang; Chih-Han Lin; Horng-Huei Tseng
- Web page: https://patentgrep.com/patent/US10872890B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate, a core device disposed above the substrate, and an input/output (I/O) device disposed above the substrate. The core device includes a first gate electrode having a bottom surface and a sidewall that define a first interior angle therebetween. The first interior angle is an obtuse angle. The I/O device includes a second gate electrode having a bottom surface and a sidewall that define a second interior angle therebetween. The second interior angle is greater than the first interior angle.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a core device over the substrate and comprising a first gate electrode having a bottom surface and a sidewall, wherein the bottom surface of the first gate electrode and the sidewall of the first gate electrode define inside the first gate electrode a first interior angle, and the first interior angle is an obtuse angle; and
an input/output (I/O) device over the substrate and comprising a second gate electrode having a bottom surface and a sidewall, wherein the bottom surface of the second gate electrode and the sidewall of the second gate electrode define inside the second gate electrode a second interior angle, and the second interior angle is greater than the first interior angle.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the bottom surface of the first gate electrode has a bottom width and the first gate electrode includes a top surface that has a top width and the top width is greater than the bottom width.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the bottom surface of the second gate electrode has a bottom width and the second gate electrode includes a top surface that has a top width and the top width is greater than the bottom width.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the I/O device further comprises a spacer on the sidewall of the second gate electrode, and a bottom width of a bottom surface of the spacer is greater than a top width of a top surface of the spacer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the core device further comprises a spacer on the sidewall of the first gate electrode, and a bottom width of a bottom surface of the spacer is greater than a top width of a top surface of the spacer.

### Claim 6

A semiconductor device comprising:
a substrate;
a core device over the substrate and comprising a first gate electrode having a bottom surface and a sidewall, wherein the bottom surface of the first gate electrode and the sidewall of the first gate electrode define inside the first gate electrode a first interior angle; and
an input/output (I/O) device over the substrate and comprising a second gate electrode having a bottom surface and a sidewall, wherein the bottom surface of the second gate electrode and the sidewall of the second gate electrode define inside the second gate electrode a second interior angle, and the second interior angle and the first interior angle both are obtuse angles but have different values.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the bottom surface of the first gate electrode has a first bottom width, the bottom surface of the second gate electrode has a second bottom width, and the second bottom width is greater than the first bottom width.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the first gate electrode includes a top surface that has a first top width, the second gate electrode includes a top surface that has a second top width, and the second top width is greater than the first top width.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein a difference between widths of the bottom surface and a top surface of the second gate electrode is greater than a difference between widths of the bottom surface and a top surface of the first gate electrode.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein the second interior angle is greater than the first interior angle.

### Claim 11 (depends on 6)

The semiconductor device of claim 6, wherein the I/O device further comprises a spacer on a sidewall of the second gate electrode, and a bottom width of a bottom surface of the spacer is greater than a top width of a top surface of the spacer.

### Claim 12

A semiconductor device comprising:
a substrate;
a core device over the substrate and comprising a first gate electrode having a top surface and a bottom surface; and
an input/output (I/O) device over the substrate and comprising a second gate electrode having a top surface and a bottom surface, wherein a width of the top surface of the first gate electrode is less than a width of the top surface of the second gate electrode, and a width of the bottom surface of the second gate electrode is less than the width of the top surface of the second gate electrode.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a width of the bottom surface of the first gate electrode is smaller than the width of the top surface of the first gate electrode.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein a width of the bottom surface of the first gate electrode is greater than the width of the top surface of the first gate electrode.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein a width of the bottom surface of the first gate electrode is substantially equal to the width of the top surface of the first gate electrode.

### Claim 16 (depends on 12)

The semiconductor device of claim 12, wherein the core device further comprises a semiconductor fin disposed between the first gate electrode and the substrate.

### Claim 17 (depends on 12)

The semiconductor device of claim 12, wherein the I/O device further comprises a semiconductor fin disposed between the second gate electrode and the substrate.

### Claim 18 (depends on 12)

The semiconductor device of claim 12, wherein the I/O device further comprises a spacer on a sidewall of the second gate electrode, and a bottom width of a bottom surface of the spacer is greater than a top width of a top surface of the spacer.

### Claim 19 (depends on 12)

The semiconductor device of claim 12, wherein the core device further comprises a spacer on a sidewall of the first gate electrode, and a bottom width of a bottom surface of the spacer is greater than a top width of a top surface of the spacer.

### Claim 20 (depends on 12)

The semiconductor device of claim 12, wherein a width of the bottom surface of the first gate electrode minus the width of the top surface of the first gate electrode is greater than the width of the bottom surface of the second gate electrode minus the width of the top surface of the second gate electrode.