# US 10,872,888 B2 · Semiconductor devices and methods of fabricating the same

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- Number: US 10,872,888 B2
- Document ID: US10872888B2
- Status: Granted
- Kind: B2
- Application number: 16/432,233
- Filed: 2019-06-05
- Published: 2019-10-10
- Granted: 2020-12-22
- Earliest claimed: 2015-10-30
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Moon-Kyu Park; Jae-Yeol Song; Hoon-Joo Na; Yoon-Tae Hwang; Ki-Joong Yoon; Sang-Jin Hyun
- Web page: https://patentgrep.com/patent/US10872888B2

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6213: {having rounded corners}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 64/605: {Source, drain, or gate electrodes for FETs comprising highly resistive materials}
- H10D 64/664: {the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/834: {comprising FinFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 14/6536: {by exposure to radiation, e.g. visible light}
- H10P 14/6544: {to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

## Claims

### Claim 1

A semiconductor device comprising:
a fin-shaped active region protruding from a substrate;
a field insulating layer on the substrate, the field insulating layer being on a side of a lower portion of the fin-shaped active region and absent from an upper portion of the fin-shaped active region;
a gate insulating layer extending along an upper surface of the field insulating layer and three sides of the fin-shaped active region; and
a gate electrode structure on the gate insulating layer, the gate electrode structure comprising a silicon oxide layer spaced apart from the gate insulating layer and a barrier metal layer between the silicon oxide layer and the gate insulating layer,
wherein the three sides of the fin-shaped active region include top, right, and left sides of the fin-shaped active region, and
wherein the gate electrode structure extends on the three sides of the fin-shaped active region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the silicon oxide layer extends along a surface of the barrier metal layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the gate insulating layer comprises an interfacial layer extending along the three sides of the fin-shaped active region, and the interfacial layer comprises silicon oxide.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the gate insulating layer further comprises a high-k insulating material layer stacked on the interfacial layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the gate electrode structure further comprises a conductive layer on the silicon oxide layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a channel layer between the substrate and the gate insulating layer.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the channel layer has a lattice constant different from a lattice constant of the substrate.

### Claim 8

A semiconductor device comprising:
a fin-shaped active region protruding from a substrate;
a field insulating layer on the substrate, the field insulating layer being on a side of a lower portion of the fin-shaped active region and absent from an upper portion of the fin-shaped active region;
a first silicon oxide layer extending along a surface of the upper portion of the fin-shaped active region;
a high-k insulating layer on the first silicon oxide layer and the field insulating layer;
a barrier metal layer on the high-k insulating layer;
a second silicon oxide layer on the barrier metal layer, the barrier metal layer extending between the second silicon oxide layer and the high-k insulating layer, and the second silicon oxide layer extending along an upper surface of the field insulating layer; and
an upper gate electrode on the second silicon oxide layer, the upper gate electrode crossing the fin-shaped active region,
wherein the barrier metal layer directly contacts the second silicon oxide layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the second silicon oxide layer extends along a surface of the high-k insulating layer.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, further comprising a silicon layer between the barrier metal layer and the second silicon oxide layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the silicon layer directly contacts the barrier metal layer.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein an upper portion of the barrier metal layer is higher than a lower portion of the upper gate electrode.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the barrier metal layer is on top, left, and right sides of the fin-shaped active region.

### Claim 14

A semiconductor device comprising:
a fin-shaped active region protruding from a substrate;
a gate insulating layer on the substrate and fin-shaped active region;
a lower gate electrode on the gate insulating layer, the lower gate electrode comprising a barrier metal layer;
a silicon oxide layer on the lower gate electrode; and
an upper gate electrode on the silicon oxide layer, the upper gate electrode having a thickness different from a thickness of the lower gate electrode,
wherein the fin-shaped active region has top, right, and left sides, and
wherein the lower gate electrode, the silicon oxide layer, and the upper gate electrode extend along the top, right, and left sides of the fin-shaped active region.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the thickness of the upper gate electrode is greater than the thickness of the lower gate electrode.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, further comprising an interlayer insulating layer on the substrate,
wherein the interlayer insulating layer comprises a trench, and
wherein the gate insulating layer, the lower gate electrode, the silicon oxide layer, and the upper gate electrode extend along a sidewall and a bottom surface of the trench.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the thickness of the lower gate electrode on the sidewall of the trench is different from the thickness of the upper gate electrode on the sidewall of the trench.