# US 10,872,886 B2 · Semiconductor device including vertical routing structure and method for manufacturing the same

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- Number: US 10,872,886 B2
- Document ID: US10872886B2
- Status: Granted
- Kind: B2
- Application number: 16/725,684
- Filed: 2019-12-23
- Published: 2020-05-07
- Granted: 2020-12-22
- Earliest claimed: 2017-11-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wei-Chih Wen; Han-Ting Tsai; Chung-Te Lin
- Web page: https://patentgrep.com/patent/US10872886B2

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/01: {Manufacture or treatment}
- H10N 50/01: Manufacture or treatment
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10K 59/124: Insulating layers formed between TFT elements and OLED elements
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a transistor on a substrate, the transistor having a source region and a drain region,
wherein the source region includes:
a first via formed over the source region;
a first metal layer formed on the first via, the first metal layer extending along a first direction;
a second via formed over the first metal layer, the second via overlapping the first via; and
a second metal layer formed on the second via, the second metal layer extending along a second direction different from the first direction, and
wherein the drain region includes:
a third via formed over the drain region, the third via being at a same height level as the first via;
a third metal layer formed on the third via;
a fourth via formed over the third metal layer, the fourth via overlapping the third via; and
a controlled device formed on the fourth via, the controlled device being at a same height level as the second metal layer and controlled by the transistor.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first via and the second via have the same area in a plan view.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first metal layer connects to a controlling device which controls an applied voltage to the first metal layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second metal layer connects to a controlling device which controls an applied voltage to the second metal layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the controlled device includes one of an organic light emitting diode device, a memory and a transistor.

### Claim 6 (depends on 1)

The device of claim 1, further comprising:
a plurality of vias and metal layers formed between the first metal layer and the second via.

### Claim 7 (depends on 6)

The device of claim 6, wherein all the plurality of vias have a same shape (or area) and all the plurality of metal layers have a same shape (or area), in plan view.

### Claim 8

A semiconductor device, the device comprising:
a transistor over a substrate, the transistor having a source region and a drain region,
wherein the source region includes:
a first via surrounded by a first protective layer in a first interlayer dielectric (ILD) layer on the source region;
a first metal layer formed on the first via, the first metal layer extending along a first direction;
a second via surrounded by a second protective layer in a second ILD layer over the first metal layer, the second via overlapping the first via; and
a second metal layer formed on the second via, the second metal layer extending along a second direction different from the first direction, and
wherein the drain region includes:
a third via surrounded by a third protective layer in the first ILD layer over the drain region, the third via being at a same height level as the first via;
a third metal layer formed on the third via;
a fourth via surrounded by a fourth protective layer in the second ILD layer over the third metal layer, the fourth via overlapping the third via; and
a controlled device disposed on the fourth via, the controlled device being at a same height level as the second metal layer and controlled by the transistor.

### Claim 9 (depends on 8)

The device of claim 8, wherein the first via and the second via have the same area in a plan view.

### Claim 10 (depends on 8)

The device of claim 8, wherein the first and second protective layers are formed of titanium nitride or tantalum nitride.

### Claim 11 (depends on 8)

The device of claim 8, wherein the first metal layer connects to a controlling device which controls an applied voltage to the first metal layer.

### Claim 12 (depends on 8)

The device of claim 8, wherein the second metal layer connects to a controlling device which controls an applied voltage to the second metal layer.

### Claim 13 (depends on 8)

The device of claim 8, wherein the controlled device includes one of an organic light emitting diode device, a memory and a transistor.

### Claim 14 (depends on 8)

The device of claim 8, further comprising:
a plurality of vias and metal layers formed between the first metal layer and the second via.

### Claim 15 (depends on 14)

The device of claim 14, wherein all the plurality of vias have a same shape and all the plurality of metal layers have a same shape, in plan view.

### Claim 16

A semiconductor device, the device comprising:
a transistor on a substrate, the transistor having a source region and a drain region 140;
a member including:
an interlayer dielectric layer;
a source-side via in the interlayer dielectric layer formed over the source region and a drain-side via in the interlayer dielectric layer over the drain region; and
a source-side metal layer in contact with the source-side via and a drain-side metal layer in contact with the source-side via, and
a controlled device on one of an uppermost source-side via and an uppermost drain-side via formed with the member stacked,
wherein a second interlayer dielectric layer in contact with the drain-side metal layer is made of a second semiconductor material different from a first semiconductor material of a first interlayer dielectric layer in contact with the drain-side via.

### Claim 17 (depends on 16)

The device of claim 16, wherein:
the controlled device is formed on the uppermost drain-side via, and
at least one of source-side metal layers is coupled to a logic device.

### Claim 18 (depends on 17)

The device of claim 17, wherein none of drain-side metal layers is coupled to the logic device.

### Claim 19 (depends on 16)

The device of claim 16, wherein the controlled device is a memory cell.

### Claim 20 (depends on 19)

The device of claim 19, wherein the memory cell is one of a phase change memory cell and a resistance change memory cell.