# US 10,872,885 B2 · Integrated circuit packages and methods of forming same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,885 B2 - Document ID: US10872885B2 - Status: Granted - Kind: B2 - Application number: 15/946,885 - Filed: 2018-04-06 - Published: 2019-01-03 - Granted: 2020-12-22 - Earliest claimed: 2017-06-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Yi-Wen Wu; Hung-Jui Kuo; Ming-Che Ho - Web page: https://patentgrep.com/patent/US10872885B2 ## CPC - H10D 88/00: Three-dimensional [3D] integrated devices - G01R 31/2886: {Features relating to contacting the IC under test, e.g. probe heads; chucks (G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06)} - G01R 31/2896: {Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00)} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 88/01: {Manufacture or treatment} - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 90/00: Package configurations - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/0198: {batch processes} - H10W 72/29: Bond pads specially adapted therefor - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/014: {using batch processing} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening. ## Claims ### Claim 1 A method comprising: forming an insulating layer over a carrier; attaching a first side of an integrated circuit die to the insulating layer; forming an encapsulant over and around the integrated circuit die; patterning the encapsulant to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die, the first opening extending through the encapsulant and exposing the insulating layer, the second opening exposing a second side of the integrated circuit die, the first side of the integrated circuit die being opposite the second side of the integrated circuit die; and simultaneously depositing a conductive material in the first opening and the second opening, wherein a bottommost point of the conductive material is above a topmost point of the insulating layer. ### Claim 2 (depends on 1) The method of claim 1, further comprising: removing the carrier from the first side of the integrated circuit die; and forming a redistribution structure over the first side of the integrated circuit die. ### Claim 3 (depends on 1) The method of claim 1, wherein the conductive material partially fills the first opening. ### Claim 4 (depends on 3) The method of claim 3, wherein a thickness of the conductive material over a bottom of the first opening is greater than a thickness of the conductive material along sidewalls of the first opening. ### Claim 5 (depends on 1) The method of claim 1, wherein the conductive material overfills the second opening. ### Claim 6 (depends on 1) The method of claim 1, further comprising, after simultaneously depositing the conductive material in the first opening and the second opening, depositing an insulating material in the first opening, the insulating material overfilling the first opening. ### Claim 7 A method comprising: attaching a first side of an integrated circuit die to an insulating layer on a carrier, a second side of the integrated circuit die having a contact pad, the first side of the integrated circuit die being opposite the second side of the integrated circuit die; forming an encapsulant over and around the integrated circuit die; and simultaneously forming a conductive via and a first redistribution layer (RDL) in the encapsulant, the conductive via being laterally spaced apart from a sidewall of the integrated circuit die, a top surface of the conductive via being below a topmost surface of the encapsulant, a bottommost point of the conductive via being level with a bottommost point of the encapsulant, the first RDL being over the second side of the integrated circuit die, the first RDL being in electrical contact with the contact pad, wherein simultaneously forming the conductive via and the first RDL in the encapsulant comprises: patterning the encapsulant to form a first opening and a second opening in the encapsulant, the first opening extending through the encapsulant and exposing a topmost surface of the insulating layer, the second opening exposing the second side of the integrated circuit die; forming a patterned mask over the encapsulant, the patterned mask exposing the first opening and the second opening; and simultaneously non-conformally depositing a conductive material in the first opening and the second opening through the patterned mask, wherein a bottommost point of the conductive material is above the bottommost point of the encapsulant. ### Claim 8 (depends on 7) The method of claim 7, further comprising: detaching the carrier from the first side of the integrated circuit die; and forming a second RDL over the first side of the integrated circuit die. ### Claim 9 (depends on 7) The method of claim 7, wherein a thickness of the conductive material over a bottom of the first opening is greater than a thickness of the conductive material along sidewalls of the first opening. ### Claim 10 (depends on 7) The method of claim 7, wherein a thickness of the conductive material over a bottom of the first opening is less than a height of the integrated circuit die. ### Claim 11 (depends on 7) The method of claim 7, wherein the encapsulant comprises a photo-patternable insulating material. ### Claim 12 A method comprising: depositing a first insulating layer over a carrier; attaching a first side of an integrated circuit die to the first insulating layer, a second side of the integrated circuit die having a contact pad, the first side of the integrated circuit die being opposite the second side of the integrated circuit die; depositing a second insulating layer over the first insulating layer, the second insulating layer extending along a sidewall of the integrated circuit die and covering the contact pad of the integrated circuit die; and simultaneously forming a conductive column in the second insulating layer and a first redistribution layer (RDL) over the contact pad of the integrated circuit die, the conductive column extending through the second insulating layer and physically contacting the first insulating layer, a portion of the first RDL extending into the second insulating layer and physically contacting the contact pad of the integrated circuit die, wherein simultaneously forming the conductive column in the second insulating layer and the first RDL over the contact pad of the integrated circuit die comprises: patterning the second insulating layer to form a first opening and a second opening in the second insulating layer, the first opening exposing a topmost surface of the first insulating layer, the second opening exposing the contact pad of the integrated circuit die; and simultaneously non-conformally depositing a conductive material in the first opening and the second opening, wherein a bottommost point of the conductive material is above a topmost point of the first insulating layer. ### Claim 13 (depends on 12) The method of claim 12, further comprising: depositing a third insulating layer over the conductive column and the first RDL, a portion of the third insulating layer deposited over the conductive column extending below a topmost surface of the second insulating layer; and forming a second RDL over the third insulating layer, a portion of the second RDL extending into the third insulating layer and physically contacting the first RDL. ### Claim 14 (depends on 13) The method of claim 13, wherein a portion of the conductive column is interposed between a sidewall of the second insulating layer and a sidewall of the third insulating layer. ### Claim 15 (depends on 12) The method of claim 12, further comprising: detaching the carrier from the first insulating layer; and forming a second RDL over the first insulating layer, a portion of the second RDL extending through the first insulating layer and physically contacting the conductive column. ### Claim 16 (depends on 12) The method of claim 12, wherein the conductive material partially fills the first opening and overfills the second opening. ### Claim 17 (depends on 7) The method of claim 7, wherein simultaneously forming the conductive via and the first RDL in the encapsulant further comprises, after simultaneously non-conformally depositing the conductive material in the first opening and the second opening through the patterned mask, removing the patterned mask. ### Claim 18 (depends on 12) The method of claim 12, wherein simultaneously forming the conductive column in the second insulating layer and the first RDL over the contact pad of the integrated circuit die further comprises, before simultaneously non-conformally depositing the conductive material in the first opening and the second opening, forming a patterned mask over the second insulating layer, the patterned mask exposing the first opening and the second opening. ### Claim 19 (depends on 4) The method of claim 4, wherein the thickness of the conductive material over the bottom of the first opening is between about 12 μm and about 60 μm, and wherein the thickness of the conductive material along sidewalls of the first opening is between about 2 μm and about 10 μm. ### Claim 20 (depends on 7) The method of claim 7, wherein the encapsulant comprises a polymer material.