# US 10,872,884 B2 · Electrostatic discharge handling for lateral transistor devices

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- Number: US 10,872,884 B2
- Document ID: US10872884B2
- Status: Granted
- Kind: B2
- Application number: 16/848,637
- Filed: 2020-04-14
- Published: 2020-07-30
- Granted: 2020-12-22
- Earliest claimed: 2018-09-17
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Han-Chung Tai
- Web page: https://patentgrep.com/patent/US10872884B2

## CPC

- H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices}
- H10D 30/83: FETs having PN junction gate electrodes
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/111: {Field plates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor transistor device includes a source region, a gate region having a p-type gate region and an n-type gate region, and a drain region having a p-type drain region and an n-type drain region. The p-type gate region, the n-type gate region, the p-type drain region, and the n-type drain region are positioned to provide, in response to an electrostatic discharge (ESD) voltage, a drain-to-gate ESD current path to at least partially discharge the ESD voltage.

## Claims

### Claim 1

A method of making a semiconductor transistor device, the method comprising:
forming a source region;
forming a gate region having a p-type gate region and an n-type gate region;
forming a drain region having a p-type drain region and an n-type drain region;
forming a p-well at least partially under the gate region, and electrically shorted to the p-type gate region during an electrostatic discharge (ESD); and
forming an n-well under the source region, the gate region, the p-well, and the drain region, and electrically shorted to the n-type drain region during the ESD.

### Claim 2 (depends on 1)

The method of claim 1, comprising:
forming a part of a Silicon Controlled Rectifier (SCR) using the p-type gate region, the n-type gate region, the p-type drain region, and the n-type drain region form.

### Claim 3 (depends on 2)

The method of claim 2, wherein the p-type drain region is larger than the n-type drain region.

### Claim 4 (depends on 3)

The method of claim 3, comprising:
forming a part of a PNPN structure of the SCR using the p-type gate region, the n-type gate region, the p-type drain region, and the n-type drain region.

### Claim 5 (depends on 1)

The method of claim 1, comprising:
forming the p-type gate region, the n-type gate region, the p-type drain region, and the n-type drain region in positions to provide, in response to the ESD, a drain-to-gate ESD current path to at least partially discharge the ESD.

### Claim 6 (depends on 1)

The method of claim 1, comprising:
forming the drain region at a center portion of the semiconductor transistor device;
forming the gate region around and surrounding the drain region; and
forming the source region around and surrounding the gate region.

### Claim 7 (depends on 6)

The method of claim 6, comprising:
forming an ESD guard ring structure around and surrounding the source region.

### Claim 8 (depends on 7)

The method of claim 7, wherein the ESD guard ring structure provides a secondary ESD current path to the drain-to-gate ESD current path.

### Claim 9 (depends on 1)

The method of claim 1, wherein the semiconductor transistor device includes a lateral junction field effect transistor (lateral JFET).

### Claim 10 (depends on 1)

The method of claim 1, wherein the semiconductor transistor devices includes a lateral metal oxide semiconductor field effect transistor (lateral MOSFET).

### Claim 11 (depends on 1)

The method of claim 1, comprising:
forming the n-type drain region and the p-type drain region as pillar structures.

### Claim 12

A method of making a semiconductor transistor device, comprising:
forming, in a substrate of a first conductivity type, a first well region of a second conductivity type;
forming a source region of the second conductivity type in the first well region;
forming a second well region of the first conductivity type in the first well region;
forming a first gate region having the first conductivity type and in the second well region as part of a gate region;
forming a second gate region having the second conductivity type in the second well region as part of the gate region;
forming a first drain region having the second conductivity type in the first well region as part of a drain region; and
forming a second drain region having the first conductivity type in the first well region as part of the drain region,
wherein at least the second drain region, the first well region, the second well region, and the second gate region form a structure that provides, in response to voltage induced by electrostatic discharge (ESD), a drain-to-gate ESD current path.

### Claim 13 (depends on 12)

The method of claim 12, comprising:
forming the first well region at least partially under the gate region, and electrically shorted to the first gate region during the ESD; and
forming the second well region including a high-voltage well formed under the source region, the gate region, the first well region, and the drain region, and electrically shorted to the second drain region during the ESD.

### Claim 14 (depends on 12)

The method of claim 12, comprising:
forming the drain region at a center portion of the semiconductor transistor device,
forming the gate region around and surrounding the drain region; and
forming the source region around and surrounding the gate region.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
forming an ESD guard ring structure around and surrounding the source region.

### Claim 16 (depends on 15)

The method of claim 15, wherein the ESD guard ring structure provides a secondary ESD current path to the drain-to-gate ESD current path.

### Claim 17

A method of making a semiconductor transistor device, the method comprising:
forming a source region;
forming a first gate region having a first conductivity type, as part of a gate region;
forming a second gate region having a second conductivity type, as part of the gate region;
forming a first drain region having the second conductivity type, as part of a drain region; and
forming a second drain region having the first conductivity type, as part of the drain region,
forming the drain region at a center portion of the semiconductor transistor device,
forming the gate region around and surrounding the drain region; and
forming the source region around and surrounding the gate region.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming, in a substrate of the first conductivity type, a first well region of the second conductivity type;
forming the source region of the second conductivity type in the first well region;
forming a second well region of the first conductivity type in the first well region;
forming the first gate region having the first conductivity type in the second well region;
forming the second gate region having the second conductivity type in the second well region;
forming the first drain region having the second conductivity type in the first well region; and
forming the second drain region having the first conductivity type in the first well region.

### Claim 19 (depends on 17)

The method of claim 17, wherein at least the second drain region, the first well region, the second well region, and the second gate region form a structure in response to an electrostatic discharge (ESD) voltage, and conduct a drain-to-gate ESD current path to at least partially discharge the ESD voltage.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
forming an ESD guard ring structure around and surrounding the source region, wherein the ESD guard ring structure provides a secondary ESD current path to the drain-to-gate ESD current path.