# US 10,872,879 B2 · Semiconductor package and manufacturing method thereof

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- Number: US 10,872,879 B2
- Document ID: US10872879B2
- Status: Granted
- Kind: B2
- Application number: 16/037,686
- Filed: 2018-07-17
- Published: 2018-11-08
- Granted: 2020-12-22
- Earliest claimed: 2015-11-12
- Assignees: Amkor Technology Singapore Holding Pte. Ltd.
- Applicants: Amkor Technology Singapore Holding Pte. Ltd.
- Inventors: Jin Seong Kim; Edwin J. Adlam; Ludovico E. Bancod; Gi Jung Kim; Robert Lanzone; Jae Ung Lee; Yung Woo Lee; Mi Kyeong Choi
- Web page: https://patentgrep.com/patent/US10872879B2

## CPC

- H10W 90/00: Package configurations
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 74/01: Manufacture or treatment
- H10W 74/10: characterised by their shape or disposition
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 42/271: {the arrangements being between stacked chips}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/682: {comprising holes having chips therein}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/014: {using batch processing}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.

## Claims

### Claim 1

A method of manufacture comprising:
providing a substrate having:
a substrate top surface having a substrate top first pad and a substrate top second pad,
a substrate bottom surface having a substrate third pad and a substrate interconnect pad, and
a substrate lateral surface;
providing a first device on the substrate top surface and coupled to the substrate top first pad, the first device comprising:
a first device bottom surface facing the substrate top surface,
a first device lateral surface, and
a first device top surface facing away from the substrate top surface;
providing a second device component coupled to the substrate top second pad;
providing a first encapsulant to encapsulate the substrate top surface, the first device, and the second device,
the first encapsulant having:
a first encapsulant top surface, and
a first encapsulant lateral surface;
attaching a third device to the substrate third pad on the substrate bottom surface, the third device comprising:
a third device top surface facing the substrate bottom surface,
a third device lateral surface, and
a third device bottom surface facing away from the substrate bottom surface;
providing a first interconnect on the substrate bottom surface and coupled to the substrate interconnect pad,
the first interconnect comprising an interconnect protruded section and providing external interface to the semiconductor package;
and
applying a second encapsulant to encapsulate the substrate bottom surface and at least partially the third device and the first interconnect, the second encapsulant comprising:
a second encapsulant bottom surface, and
a second encapsulant lateral surface;
wherein:
the interconnect protruded section protrudes past the second encapsulant bottom surface;
at least one of the first, second, or third devices is an electronic device; and
at least one of the first, second, or third devices is a passive component.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the third device is a thinned device, with its third device bottom surface planarized, such that the first device lateral surface is at least 1.6 times vertically greater than the third device lateral surface.

### Claim 3 (depends on 1)

The method of claim 1, wherein:
attaching the third device comprises:
attaching the third device having a third device initial bottom;
providing the first interconnect comprises:
providing the first interconnect having a first interconnect initial bottom;
providing the second encapsulant comprises:
providing the second encapsulant having a second encapsulant initial bottom;
wherein a height of the second encapsulant initial bottom is:
greater than a height of the third device initial bottom; and
greater than a height of the first interconnect initial bottom.

### Claim 4 (depends on 3)

The method of claim 3, wherein:
the height of the third device initial bottom is greater than the height of the first interconnect initial bottom.

### Claim 5 (depends on 1)

The method of claim 1, comprising:
thinning the third device, the first interconnect, and the second encapsulant to reveal, coplanar to each other:
the third device bottom surface;
a first interconnect intermediate surface; and
the second encapsulant bottom surface.

### Claim 6 (depends on 1)

The method of claim 1, comprising:
thinning the first interconnect and the second encapsulant to reveal, coplanar to each other:
a first interconnect intermediate surface; and
the second encapsulant bottom surface.

### Claim 7 (depends on 6)

The method of claim 6, comprising:
attaching a first interconnect distal portion to the first interconnect intermediate surface,
wherein the first interconnect comprises a first interconnect inner portion bounded by the second encapsulant between the first interconnect intermediate surface and the substrate.

### Claim 8 (depends on 7)

The method of claim 7, comprising:
reflowing the first interconnect inner portion and the first interconnect distal portion together to define the first interconnect, such that the first interconnect protruded section protrudes past the second encapsulant bottom surface by at least 50 μm.

### Claim 9 (depends on 8)

The method of claim 8, wherein:
prior to the thinning, the first interconnect comprises a first interconnect initial height; and
after the reflowing, a combined final height of the first interconnect inner portion and of the first interconnect distal portion is within 5% of the first interconnect initial height.

### Claim 10 (depends on 7)

The method of claim 7, wherein:
a volume of the first interconnect inner portion is greater than a volume of the first interconnect distal portion.

### Claim 11 (depends on 1)

The method of claim 1, comprising:
thinning the first interconnect and the second encapsulant coplanar to each other; and
ablating into the second encapsulant after the thinning, comprising:
forming a via wall that extends from the second encapsulant bottom surface towards the substrate bottom surface and defines a volume that bounds an interconnect bounded section of the first interconnect:
wherein the via wall is spaced apart from the interconnect bounded section.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
a diameter defined by an opening of the via wall is greater than a diameter defined by a base of the via wall.

### Claim 13 (depends on 11)

The method of claim 11, wherein:
the ablating into the second encapsulant comprises:
forming a via ledge that extends from the first interconnect to the via wall and defines a via ledge plane substantially parallel to the encapsulant bottom surface;
and
the first interconnect comprises:
an interconnect encapsulated section in contact with the second encapsulant and extending between the via ledge plane and the substrate bottom surface.

### Claim 14 (depends on 1)

The method of claim 1, wherein:
the third device is a thinned device, with its third device bottom surface planarized, such that the third device lateral surface is up to approximately 60 μm vertically.

### Claim 15 (depends on 1)

The method of claim 1, wherein:
the third device is a thinned device, with its third device bottom surface planarized, such that the substrate lateral surface is vertically at least 2 times the third device lateral surface.

### Claim 16 (depends on 1)

The method of claim 1, wherein:
a bump couples the third device to the substrate bottom surface and defines a bump gap between the third device top surface and the substrate bottom surface; and
the third device is a thinned device, with its third device bottom surface planarized, such that the third device lateral surface is vertically at most twice the bump gap.

### Claim 17

A method of manufacture comprising:
providing a substrate having
a substrate top surface having a substrate top first pad and a substrate top second pad,
a substrate bottom surface having a substrate third pad and a substrate interconnect pad, and
a substrate lateral surface;
providing a first device on the substrate top surface and coupled to the substrate top first pad, the first device comprising:
a first device bottom surface facing the substrate top surface,
a first device lateral surface, and
a first device top surface facing away from the substrate top surface;
providing a second device component coupled to the substrate top second pad;
providing a first encapsulant that encapsulates the substrate top surface, the first device, and the second device,
the first encapsulant having:
a first encapsulant top surface, and
a first encapsulant lateral surface;
providing a third device on the substrate bottom surface and coupled to the substrate third pad, the third device comprising:
a third device top surface facing the substrate bottom surface,
a third device lateral surface, and
a third device bottom surface facing away from the substrate bottom surface;
providing a first interconnect on the substrate bottom surface and coupled to the substrate interconnect pad,
the first interconnect comprising an interconnect protruded section and providing external interface to the semiconductor package;
providing a second encapsulant that encapsulates the substrate bottom surface and at least partially the third device and the first interconnect, the second encapsulant comprising:
a second encapsulant bottom surface, and
a second encapsulant lateral surface;
and
providing a first electromagnetic interference (EMI) shield that bounds at least:
the first encapsulant top surface,
the first encapsulant lateral surface, and
the substrate lateral surface;
wherein:
the third device bottom surface is exposed from the second encapsulant;
the interconnect protruded section protrudes past the second encapsulant bottom surface;
at least one of the first, second, or third devices is an electronic device; and
at least one of the first, second, or third devices is a passive component.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
providing a bottom electromagnetic interference (EMI) shield that:
surrounds the third device lateral surface;
extends through the second encapsulant, from the substrate bottom surface toward the second encapsulant bottom surface; and
is exclusive of sheet metal.

### Claim 19 (depends on 1)

The method of claim 1, further comprising providing a first electromagnetic interference (EMI) shield that bounds at least:
a portion of the first encapsulant top surface, and
a portion of the first encapsulant lateral surface.

### Claim 20 (depends on 1)

The method of claim 1, wherein the third device bottom surface is exposed from the second encapsulant.