# US 10,872,872 B2 · Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,872 B2 - Document ID: US10872872B2 - Status: Granted - Kind: B2 - Application number: 16/347,188 - Filed: 2016-12-30 - Published: 2019-11-28 - Granted: 2020-12-22 - Earliest claimed: 2016-12-30 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Robert Alan May; Sri Ranga Sai Boyapati; Kristof Kuwawi Darmawikarta; Srinivas V. Pietambaram; Javier Soto Gonzalez; Kwangmo Chris Lim; Aleksandar Aleksov - Web page: https://patentgrep.com/patent/US10872872B2 ## CPC - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/42: Vias, e.g. via plugs - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/68: Shapes or dispositions thereof - H10W 70/685: comprising multiple insulating layers - H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/00: Package configurations - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented. ## Claims ### Claim 1 An integrated circuit package, comprising: a package substrate having a first face and an opposing second face, wherein the package substrate includes a plurality of layers; a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers of the package substrate, wherein an input/output (I/O) of the high-density interconnect layer is between 100 and 1000 I/O/mm/layer, wherein the high-density interconnect layer is at the first face of the package substrate, and wherein the high-density interconnect layer includes: a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 μm and 80 μm; and a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via; and a first die, wherein the first die is electrically coupled to the package substrate via the pillar on the high-density interconnect layer. ### Claim 2 (depends on 1) The integrated circuit package of claim 1, wherein the first die is electrically coupled to the pillar. ### Claim 3 (depends on 1) The integrated circuit package of claim 1, wherein the package substrate is electrically coupled to the via. ### Claim 4 (depends on 1) The integrated circuit package of claim 1, further comprising: a cavity formed on the package substrate. ### Claim 5 (depends on 4) The integrated circuit package of claim 4, further comprising: a second die in the cavity formed on the package substrate, wherein the second die is conductively connected to the package substrate. ### Claim 6 (depends on 5) The integrated circuit package of claim 5, further comprising: a third die in the cavity formed on the package substrate, wherein the third die is conductively connected to the second die. ### Claim 7 (depends on 1) The integrated circuit package of claim 1, wherein an input/output (I/O) of an individual layer of the plurality of layers of the package substrate, that is not the high-density interconnect layer, is between 15 and 60 I/O/mm/layer. ### Claim 8 A computing device, comprising: a circuit board; and an integrated circuit package coupled to the circuit board, wherein the integrated circuit package comprises: a package substrate having a first face and an opposing second face, wherein the package substrate includes a plurality of layers; a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers of the package substrate, wherein an input/output (I/O) of the high-density interconnect layer is between 100 and 1000 I/O/mm/layer, wherein the high-density interconnect layer is at the first face of the package substrate, and wherein the high-density interconnect layer includes: a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 μm and 80 μm; and a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via; a first die, wherein the first die is electrically coupled to the package substrate via one or more of the plurality of pillars on the high-density interconnect layer. ### Claim 9 (depends on 8) The computing device of claim 8, wherein the first die is electrically coupled to the one or more of the plurality of pillars. ### Claim 10 (depends on 8) The computing device of claim 8, wherein the package substrate is electrically coupled to the via. ### Claim 11 (depends on 8) The computing device of claim 8, further comprising: a cavity formed on the package substrate. ### Claim 12 (depends on 11) The computing device of claim 11, further comprising: a second die in the cavity formed on the package substrate, wherein the second die is conductively connected to the package substrate. ### Claim 13 (depends on 12) The computing device of claim 12, further comprising: a third die in the cavity formed on the package substrate, wherein the third die is conductively connected to the second die. ### Claim 14 An integrated circuit assembly, comprising: a package substrate having a first face and an opposing second face, wherein the package substrate includes a plurality of layers; and a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers of the package substrate, wherein an input/output (I/O) of the high-density interconnect layer is between 100 and 1000 I/O/mm/layer, wherein the high-density interconnect layer is at the first face of the package substrate, and wherein the high-density interconnect layer includes: a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 μm and 80 μm; and a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via. ### Claim 15 (depends on 14) The integrated circuit assembly of claim 14, wherein an I/O of the next individual layer of the plurality of layers of the package substrate is between 15 and 60 I/O/mm/layer. ### Claim 16 (depends on 14) The integrated circuit assembly of claim 14, wherein the first face of the package substrate is an active side and the second face of the package substrate is a back side, and wherein the back side has a bump pitch between 200 um and 1000 um. ### Claim 17 (depends on 14) The integrated circuit assembly of claim 14, wherein the high-density interconnect layer further includes a pad formed on the second side of the high-density interconnect layer and the pad has a pad size between 1 um and 24 um.