# US 10,872,871 B2 · Chip package structure with dummy bump and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,871 B2 - Document ID: US10872871B2 - Status: Granted - Kind: B2 - Application number: 16/405,429 - Filed: 2019-05-07 - Published: 2020-06-25 - Granted: 2020-12-22 - Earliest claimed: 2018-12-21 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Sung-Hui Huang; Kuan-Yu Huang; Shang-Yun Hou; Yushun Lin; Heh-Chang Huang; Shu-Chia Hsu; Pai-Yuan Li; Kung-Chen Yeh - Web page: https://patentgrep.com/patent/US10872871B2 ## CPC - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 20/42: Vias, e.g. via plugs - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/635: {Through-vias} - H10W 72/90: Bond pads, in general - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/652: Cross-sectional shapes - H10W 72/01208: {using permanent auxiliary members, e.g. using solder flow barriers, spacers or alignment marks} - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/01251: {Changing the shapes of bumps} - H10W 72/01255: {by using masks} - H10W 72/019: {of bond pads} - H10W 72/01931: {using blanket deposition} - H10W 72/01953: {by etching} - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 72/07253: {changes in shapes} - H10W 72/07254: {changes in dispositions} - H10W 72/073: {of die-attach connectors} - H10W 72/07302: {using an auxiliary member} - H10W 72/07353: {changes in shapes} - H10W 72/07354: {changes in dispositions} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/237: {Multiple bump connectors having different shapes} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps} - H10W 72/267: {Multiple bump connectors having different functions} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/334: {Cross-sectional shape, i.e. in side view} - H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/354: {comprising polymers} - H10W 72/383: {Reinforcing structures, e.g. collars} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/983: {Reinforcing structures, e.g. collars} - H10W 74/014: {using batch processing} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/00: Package configurations - H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a dummy bump over a second surface of the first substrate. The first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip. The method includes cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump. The cut dummy bump is over a corner portion of the cut substrate, a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate, and a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate. ## Claims ### Claim 1 A method for forming a chip package structure, comprising: bonding a chip to a first surface of a first substrate; forming a dummy bump over a second surface of the first substrate, wherein the first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip; and cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump, wherein the cut dummy bump is over a corner portion of the cut substrate, a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate, and a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate. ### Claim 2 (depends on 1) The method for forming the chip package structure as claimed in claim 1, wherein the first sidewall is adjacent to the third sidewall, and the second sidewall is adjacent to the fourth sidewall. ### Claim 3 (depends on 1) The method for forming the chip package structure as claimed in claim 1, further comprising: forming a dummy solder layer over the dummy bump before cutting through the first substrate and the dummy bump, wherein the cutting through of the first substrate and the dummy bump further comprises cutting through the dummy solder layer to form a cut dummy solder layer. ### Claim 4 (depends on 3) The method for forming the chip package structure as claimed in claim 3, further comprising: reflowing the cut dummy solder layer to form a dummy solder ball. ### Claim 5 (depends on 4) The method for forming the chip package structure as claimed in claim 4, wherein the dummy solder ball has an L-like shape or a substantially quarter-circle shape in a top view of the dummy solder ball. ### Claim 6 (depends on 1) The method for forming the chip package structure as claimed in claim 1, further comprising: forming a bump over the second surface of the first substrate during forming the dummy bump over the second surface, wherein the bump is electrically connected to the chip. ### Claim 7 (depends on 6) The method for forming the chip package structure as claimed in claim 6, wherein the dummy bump is thinner than the bump. ### Claim 8 (depends on 6) The method for forming the chip package structure as claimed in claim 6, further comprising: forming a solder layer and a dummy solder layer respectively over the bump and the dummy bump before cutting through the first substrate and the dummy bump, wherein the dummy solder layer is thinner than the solder layer, and the cutting through of the first substrate and the dummy bump further comprises cutting through the dummy solder layer to form a cut dummy solder layer. ### Claim 9 (depends on 8) The method for forming the chip package structure as claimed in claim 8, further comprising: reflowing the solder layer and the cut dummy solder layer to respectively form a solder ball and a dummy solder ball after cutting through the first substrate, the dummy bump, and the dummy solder layer, wherein the dummy solder ball is thinner than the solder ball. ### Claim 10 (depends on 9) The method for forming the chip package structure as claimed in claim 9, further comprising: bonding the cut substrate to a second substrate through the solder ball. ### Claim 11 (depends on 10) The method for forming the chip package structure as claimed in claim 10, wherein the dummy solder ball is spaced apart from the second substrate, and the dummy solder ball is electrically insulated from the second substrate. ### Claim 12 A method for forming a chip package structure, comprising: bonding a chip to a first surface of a first substrate; forming a bump and a dummy bump over a second surface of the first substrate, wherein the first surface is opposite the second surface, the bump is electrically connected to the chip, and the dummy bump is electrically insulated from the chip; cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump, wherein the cut dummy bump is over a corner portion of the cut substrate, and a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate; and bonding the cut substrate to a second substrate through the bump and the dummy bump. ### Claim 13 (depends on 12) The method for forming the chip package structure as claimed in claim 12, wherein a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate. ### Claim 14 (depends on 12) The method for forming the chip package structure as claimed in claim 12, further comprising: forming a solder layer and a dummy solder layer respectively over the bump and the dummy bump before cutting through the first substrate and the dummy bump, wherein the cutting through of the first substrate and the dummy bump further comprises cutting through the dummy solder layer to form a cut dummy solder layer. ### Claim 15 (depends on 14) The method for forming the chip package structure as claimed in claim 14, further comprising: reflowing the solder layer and the cut dummy solder layer to respectively form a solder ball and a dummy solder ball after cutting through the first substrate, the dummy bump, and the dummy solder layer. ### Claim 16 A method for forming a chip package structure, comprising: bonding a chip to a first surface of a first substrate; forming a dummy bump over a second surface of the first substrate, wherein the first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip; forming a dummy solder layer over the dummy bump; cutting through the first substrate, the dummy bump, and the dummy solder layer to form a cut substrate, a cut dummy bump, and a cut dummy solder layer, wherein the cut dummy bump and the cut dummy solder layer are over a corner portion of the cut substrate, and sidewalls of the cut substrate, the cut dummy bump, and the cut dummy solder layer are substantially coplanar; and reflowing the cut dummy solder layer to form a dummy solder ball, wherein the dummy solder ball has a curved sidewall in a top view of the dummy solder ball. ### Claim 17 (depends on 16) The method for forming the chip package structure as claimed in claim 16, further comprising: forming a bump over the second surface of the first substrate during forming the dummy bump over the second surface, wherein the bump is electrically connected to the chip; forming a solder layer over the bump during forming the dummy solder layer over the dummy bump; and reflowing the solder layer to form a solder ball during reflowing the dummy solder layer to form a dummy solder ball. ### Claim 18 (depends on 17) The method for forming the chip package structure as claimed in claim 17, wherein the dummy bump is thinner than the bump, the dummy solder layer is thinner than the solder layer, and the dummy solder ball is thinner than the solder ball. ### Claim 19 (depends on 18) The method for forming the chip package structure as claimed in claim 18, further comprising: bonding the cut substrate to a second substrate through the solder ball. ### Claim 20 (depends on 19) The method for forming the chip package structure as claimed in claim 19, wherein the dummy solder ball is spaced apart from the second substrate, and the dummy solder ball is electrically insulated from the second substrate.